forked from luck/tmp_suning_uos_patched
782d59c5df
Pull irq updates from Thomas Gleixner:
"The irq departement delivers:
- a cleanup series to get rid of mindlessly copied code.
- another bunch of new pointlessly different interrupt chip drivers.
Adding homebrewn irq chips (and timers) to SoCs must provide a
value add which is beyond the imagination of mere mortals.
- the usual SoC irq controller updates, IOW my second cat herding
project"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
irqchip: gic-v3: Implement CPU PM notifier
irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling
irqchip: renesas-intc-irqpin: Add minimal runtime PM support
irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev
irqchip: atmel-aic5: Add sama5d4 support
irqchip: atmel-aic5: The sama5d3 has 48 IRQs
Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller
irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs
irqchip: renesas-irqc: Add DT binding documentation
irqchip: renesas-intc-irqpin: Document SoC-specific bindings
openrisc: Get rid of handle_IRQ
arm64: Get rid of handle_IRQ
ARM: omap2: irq: Convert to handle_domain_irq
ARM: imx: tzic: Convert to handle_domain_irq
ARM: imx: avic: Convert to handle_domain_irq
irqchip: or1k-pic: Convert to handle_domain_irq
irqchip: atmel-aic5: Convert to handle_domain_irq
irqchip: atmel-aic: Convert to handle_domain_irq
irqchip: gic-v3: Convert to handle_domain_irq
...
128 lines
2.1 KiB
Plaintext
128 lines
2.1 KiB
Plaintext
config IRQCHIP
|
|
def_bool y
|
|
depends on OF_IRQ
|
|
|
|
config ARM_GIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
|
|
config GIC_NON_BANKED
|
|
bool
|
|
|
|
config ARM_GIC_V3
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
|
|
config ARM_NVIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config ARM_VIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
|
|
config ARM_VIC_NR
|
|
int
|
|
default 4 if ARCH_S5PV210
|
|
default 2
|
|
depends on ARM_VIC
|
|
help
|
|
The maximum number of VICs available in the system, for
|
|
power management.
|
|
|
|
config ATMEL_AIC_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
select SPARSE_IRQ
|
|
|
|
config ATMEL_AIC5_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
select SPARSE_IRQ
|
|
|
|
config BRCMSTB_L2_IRQ
|
|
bool
|
|
depends on ARM
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config DW_APB_ICTL
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config IMGPDC_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config CLPS711X_IRQCHIP
|
|
bool
|
|
depends on ARCH_CLPS711X
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
select SPARSE_IRQ
|
|
default y
|
|
|
|
config OR1K_PIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config OMAP_IRQCHIP
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config ORION_IRQCHIP
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select MULTI_IRQ_HANDLER
|
|
|
|
config RENESAS_INTC_IRQPIN
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config RENESAS_IRQC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config TB10X_IRQC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config VERSATILE_FPGA_IRQ
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config VERSATILE_FPGA_IRQ_NR
|
|
int
|
|
default 4
|
|
depends on VERSATILE_FPGA_IRQ
|
|
|
|
config XTENSA_MX
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config IRQ_CROSSBAR
|
|
bool
|
|
help
|
|
Support for a CROSSBAR ip that precedes the main interrupt controller.
|
|
The primary irqchip invokes the crossbar's callback which inturn allocates
|
|
a free irq and configures the IP. Thus the peripheral interrupts are
|
|
routed to one of the free irqchip interrupt lines.
|
|
|
|
config KEYSTONE_IRQ
|
|
tristate "Keystone 2 IRQ controller IP"
|
|
depends on ARCH_KEYSTONE
|
|
help
|
|
Support for Texas Instruments Keystone 2 IRQ controller IP which
|
|
is part of the Keystone 2 IPC mechanism
|