forked from luck/tmp_suning_uos_patched
c5cfb736bc
Signed-off-by: Steven Miao <realmz6@gmail.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
/*
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* BF60x memory map
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*
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* Copyright 2011 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_MACH_MEM_MAP_H__
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#define __BFIN_MACH_MEM_MAP_H__
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#ifndef __BFIN_MEM_MAP_H__
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# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
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#endif
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/* Async Memory Banks */
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#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
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#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
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#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
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#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
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#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
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#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
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/* Boot ROM Memory */
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#define BOOT_ROM_START 0xC8000000
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#define BOOT_ROM_LENGTH 0x8000
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/* Level 1 Memory */
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/* Memory Map for ADSP-BF60x processors */
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#ifdef CONFIG_BFIN_ICACHE
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#define BFIN_ICACHESIZE (16*1024)
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#define L1_CODE_LENGTH 0x10000
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#else
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#define BFIN_ICACHESIZE (0*1024)
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#define L1_CODE_LENGTH 0x14000
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#endif
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#define L1_CODE_START 0xFFA00000
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#define L1_DATA_A_START 0xFF800000
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#define L1_DATA_B_START 0xFF900000
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#define COREA_L1_SCRATCH_START 0xFFB00000
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#define COREB_L1_SCRATCH_START 0xFF700000
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#define COREB_L1_CODE_START 0xFF600000
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#define COREB_L1_DATA_A_START 0xFF400000
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#define COREB_L1_DATA_B_START 0xFF500000
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#define COREB_L1_CODE_LENGTH 0x14000
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#define COREB_L1_DATA_A_LENGTH 0x8000
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#define COREB_L1_DATA_B_LENGTH 0x8000
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE_BANKA
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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (16*1024)
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#define BFIN_DSUPBANKS 1
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#else
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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
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#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
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#define BFIN_DCACHESIZE (32*1024)
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#define BFIN_DSUPBANKS 2
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#endif
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#else
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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
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#define L1_DATA_A_LENGTH 0x8000
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#define L1_DATA_B_LENGTH 0x8000
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#define BFIN_DCACHESIZE (0*1024)
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#define BFIN_DSUPBANKS 0
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#endif /*CONFIG_BFIN_DCACHE*/
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/* Level 2 Memory */
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#define L2_START 0xC8080000
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#define L2_LENGTH 0x40000
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#endif
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