forked from luck/tmp_suning_uos_patched
247055aa21
This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/*
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* arch/arm/include/asm/domain.h
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*
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* Copyright (C) 1999 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_DOMAIN_H
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#define __ASM_PROC_DOMAIN_H
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/*
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* Domain numbers
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*
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* DOMAIN_IO - domain 2 includes all IO only
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* DOMAIN_USER - domain 1 includes all user memory only
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* DOMAIN_KERNEL - domain 0 includes all kernel memory only
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*
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* The domain numbering depends on whether we support 36 physical
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* address for I/O or not. Addresses above the 32 bit boundary can
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* only be mapped using supersections and supersections can only
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* be set for domain 0. We could just default to DOMAIN_IO as zero,
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* but there may be systems with supersection support and no 36-bit
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* addressing. In such cases, we want to map system memory with
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* supersections to reduce TLB misses and footprint.
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*
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* 36-bit addressing and supersections are only available on
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* CPUs based on ARMv6+ or the Intel XSC3 core.
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*/
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#ifndef CONFIG_IO_36
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#define DOMAIN_KERNEL 0
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#define DOMAIN_TABLE 0
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#define DOMAIN_USER 1
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#define DOMAIN_IO 2
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#else
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#define DOMAIN_KERNEL 2
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#define DOMAIN_TABLE 2
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#define DOMAIN_USER 1
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#define DOMAIN_IO 0
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#endif
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/*
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* Domain types
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*/
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#define DOMAIN_NOACCESS 0
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#define DOMAIN_CLIENT 1
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define DOMAIN_MANAGER 3
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#else
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#define DOMAIN_MANAGER 1
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#endif
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#define domain_val(dom,type) ((type) << (2*(dom)))
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define set_domain(x) \
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do { \
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__asm__ __volatile__( \
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"mcr p15, 0, %0, c3, c0 @ set domain" \
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: : "r" (x)); \
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isb(); \
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} while (0)
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#define modify_domain(dom,type) \
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do { \
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struct thread_info *thread = current_thread_info(); \
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unsigned int domain = thread->cpu_domain; \
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domain &= ~domain_val(dom, DOMAIN_MANAGER); \
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thread->cpu_domain = domain | domain_val(dom, type); \
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set_domain(thread->cpu_domain); \
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} while (0)
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#else
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#define set_domain(x) do { } while (0)
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#define modify_domain(dom,type) do { } while (0)
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#endif
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/*
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* Generate the T (user) versions of the LDR/STR and related
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* instructions (inline assembly)
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*/
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define T(instr) #instr "t"
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#else
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#define T(instr) #instr
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#endif
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#else /* __ASSEMBLY__ */
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/*
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* Generate the T (user) versions of the LDR/STR and related
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* instructions
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*/
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#ifdef CONFIG_CPU_USE_DOMAINS
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#define T(instr) instr ## t
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#else
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#define T(instr) instr
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* !__ASM_PROC_DOMAIN_H */
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