forked from luck/tmp_suning_uos_patched
c0f3b6c777
This patch has changed command types check from data flags. MMC_STOP_TRANSMISSION is never passed to au1xmmc_send_command(). SEND_STOP() is used for MMC_STOP_TRANSMISSION. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
1025 lines
23 KiB
C
1025 lines
23 KiB
C
/*
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* linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
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*
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* Copyright (c) 2005, Advanced Micro Devices, Inc.
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*
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* Developed with help from the 2.4.30 MMC AU1XXX controller including
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* the following copyright notices:
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* Copyright (c) 2003-2004 Embedded Edge, LLC.
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* Portions Copyright (C) 2002 Embedix, Inc
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* Copyright 2002 Hewlett-Packard Company
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* 2.6 version of this driver inspired by:
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* (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
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* All Rights Reserved.
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* (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* Why is a timer used to detect insert events?
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*
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* From the AU1100 MMC application guide:
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* If the Au1100-based design is intended to support both MultiMediaCards
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* and 1- or 4-data bit SecureDigital cards, then the solution is to
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* connect a weak (560KOhm) pull-up resistor to connector pin 1.
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* In doing so, a MMC card never enters SPI-mode communications,
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* but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
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* (the low to high transition will not occur).
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*
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* So we use the timer to check the status manually.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1100_mmc.h>
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#include <asm/scatterlist.h>
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#include <au1xxx.h>
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#include "au1xmmc.h"
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#define DRIVER_NAME "au1xxx-mmc"
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/* Set this to enable special debugging macros */
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#ifdef DEBUG
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#define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
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#else
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#define DBG(fmt, idx, args...)
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#endif
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const struct {
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u32 iobase;
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u32 tx_devid, rx_devid;
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u16 bcsrpwr;
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u16 bcsrstatus;
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u16 wpstatus;
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} au1xmmc_card_table[] = {
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{ SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
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BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
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#ifndef CONFIG_MIPS_DB1200
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{ SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
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BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
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#endif
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};
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#define AU1XMMC_CONTROLLER_COUNT \
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(sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
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/* This array stores pointers for the hosts (used by the IRQ handler) */
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struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
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static int dma = 1;
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#ifdef MODULE
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module_param(dma, bool, 0);
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MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
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#endif
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static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
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{
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u32 val = au_readl(HOST_CONFIG(host));
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val |= mask;
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au_writel(val, HOST_CONFIG(host));
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au_sync();
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}
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static inline void FLUSH_FIFO(struct au1xmmc_host *host)
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{
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u32 val = au_readl(HOST_CONFIG2(host));
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au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
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au_sync_delay(1);
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/* SEND_STOP will turn off clock control - this re-enables it */
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val &= ~SD_CONFIG2_DF;
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au_writel(val, HOST_CONFIG2(host));
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au_sync();
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}
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static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
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{
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u32 val = au_readl(HOST_CONFIG(host));
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val &= ~mask;
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au_writel(val, HOST_CONFIG(host));
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au_sync();
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}
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static inline void SEND_STOP(struct au1xmmc_host *host)
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{
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/* We know the value of CONFIG2, so avoid a read we don't need */
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u32 mask = SD_CONFIG2_EN;
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WARN_ON(host->status != HOST_S_DATA);
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host->status = HOST_S_STOP;
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au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
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au_sync();
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/* Send the stop commmand */
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au_writel(STOP_CMD, HOST_CMD(host));
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}
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static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
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{
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u32 val = au1xmmc_card_table[host->id].bcsrpwr;
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bcsr->board &= ~val;
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if (state) bcsr->board |= val;
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au_sync_delay(1);
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}
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static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
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{
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return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
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? 1 : 0;
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}
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static int au1xmmc_card_readonly(struct mmc_host *mmc)
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{
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struct au1xmmc_host *host = mmc_priv(mmc);
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return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
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? 1 : 0;
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}
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static void au1xmmc_finish_request(struct au1xmmc_host *host)
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{
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struct mmc_request *mrq = host->mrq;
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host->mrq = NULL;
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host->flags &= HOST_F_ACTIVE;
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host->dma.len = 0;
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host->dma.dir = 0;
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host->pio.index = 0;
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host->pio.offset = 0;
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host->pio.len = 0;
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host->status = HOST_S_IDLE;
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bcsr->disk_leds |= (1 << 8);
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mmc_request_done(host->mmc, mrq);
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}
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static void au1xmmc_tasklet_finish(unsigned long param)
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{
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struct au1xmmc_host *host = (struct au1xmmc_host *) param;
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au1xmmc_finish_request(host);
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}
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static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
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struct mmc_command *cmd, unsigned int flags)
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{
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u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
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switch (mmc_resp_type(cmd)) {
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case MMC_RSP_NONE:
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break;
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case MMC_RSP_R1:
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mmccmd |= SD_CMD_RT_1;
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break;
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case MMC_RSP_R1B:
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mmccmd |= SD_CMD_RT_1B;
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break;
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case MMC_RSP_R2:
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mmccmd |= SD_CMD_RT_2;
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break;
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case MMC_RSP_R3:
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mmccmd |= SD_CMD_RT_3;
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break;
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default:
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printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
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mmc_resp_type(cmd));
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return MMC_ERR_INVALID;
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}
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if (flags & MMC_DATA_READ) {
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if (flags & MMC_DATA_MULTI)
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mmccmd |= SD_CMD_CT_4;
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else
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mmccmd |= SD_CMD_CT_2;
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} else if (flags & MMC_DATA_WRITE) {
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if (flags & MMC_DATA_MULTI)
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mmccmd |= SD_CMD_CT_3;
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else
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mmccmd |= SD_CMD_CT_1;
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}
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au_writel(cmd->arg, HOST_CMDARG(host));
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au_sync();
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if (wait)
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IRQ_OFF(host, SD_CONFIG_CR);
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au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
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au_sync();
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/* Wait for the command to go on the line */
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while(1) {
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if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
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break;
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}
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/* Wait for the command to come back */
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if (wait) {
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u32 status = au_readl(HOST_STATUS(host));
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while(!(status & SD_STATUS_CR))
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status = au_readl(HOST_STATUS(host));
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/* Clear the CR status */
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au_writel(SD_STATUS_CR, HOST_STATUS(host));
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IRQ_ON(host, SD_CONFIG_CR);
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}
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return MMC_ERR_NONE;
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}
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static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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{
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struct mmc_request *mrq = host->mrq;
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struct mmc_data *data;
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u32 crc;
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WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
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if (host->mrq == NULL)
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return;
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data = mrq->cmd->data;
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if (status == 0)
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status = au_readl(HOST_STATUS(host));
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/* The transaction is really over when the SD_STATUS_DB bit is clear */
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while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
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status = au_readl(HOST_STATUS(host));
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data->error = MMC_ERR_NONE;
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
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/* Process any errors */
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crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
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if (host->flags & HOST_F_XMIT)
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crc |= ((status & 0x07) == 0x02) ? 0 : 1;
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if (crc)
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data->error = MMC_ERR_BADCRC;
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/* Clear the CRC bits */
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au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
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data->bytes_xfered = 0;
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if (data->error == MMC_ERR_NONE) {
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if (host->flags & HOST_F_DMA) {
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u32 chan = DMA_CHANNEL(host);
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chan_tab_t *c = *((chan_tab_t **) chan);
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au1x_dma_chan_t *cp = c->chan_ptr;
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data->bytes_xfered = cp->ddma_bytecnt;
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}
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else
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data->bytes_xfered =
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(data->blocks * data->blksz) -
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host->pio.len;
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}
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au1xmmc_finish_request(host);
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}
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static void au1xmmc_tasklet_data(unsigned long param)
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{
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struct au1xmmc_host *host = (struct au1xmmc_host *) param;
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u32 status = au_readl(HOST_STATUS(host));
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au1xmmc_data_complete(host, status);
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}
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#define AU1XMMC_MAX_TRANSFER 8
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static void au1xmmc_send_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len, max, count = 0;
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unsigned char *sg_ptr;
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u32 status = 0;
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struct scatterlist *sg;
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data = host->mrq->data;
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if (!(host->flags & HOST_F_XMIT))
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return;
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/* This is the pointer to the data buffer */
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sg = &data->sg[host->pio.index];
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sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = data->sg[host->pio.index].length - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
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if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
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for(count = 0; count < max; count++ ) {
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unsigned char val;
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_TH))
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break;
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val = *sg_ptr++;
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au_writel((unsigned long) val, HOST_TXPORT(host));
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au_sync();
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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if (host->pio.len == 0) {
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IRQ_OFF(host, SD_CONFIG_TH);
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if (host->flags & HOST_F_STOP)
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SEND_STOP(host);
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tasklet_schedule(&host->data_task);
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}
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}
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static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len = 0, max = 0, count = 0;
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unsigned char *sg_ptr = 0;
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u32 status = 0;
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struct scatterlist *sg;
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data = host->mrq->data;
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if (!(host->flags & HOST_F_RECV))
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return;
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max = host->pio.len;
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if (host->pio.index < host->dma.len) {
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sg = &data->sg[host->pio.index];
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sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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if (sg_len < max) max = sg_len;
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}
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if (max > AU1XMMC_MAX_TRANSFER)
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max = AU1XMMC_MAX_TRANSFER;
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for(count = 0; count < max; count++ ) {
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u32 val;
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_NE))
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break;
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if (status & SD_STATUS_RC) {
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DBG("RX CRC Error [%d + %d].\n", host->id,
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host->pio.len, count);
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break;
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}
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if (status & SD_STATUS_RO) {
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DBG("RX Overrun [%d + %d]\n", host->id,
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host->pio.len, count);
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break;
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}
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else if (status & SD_STATUS_RU) {
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DBG("RX Underrun [%d + %d]\n", host->id,
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host->pio.len, count);
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break;
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}
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val = au_readl(HOST_RXPORT(host));
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if (sg_ptr)
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*sg_ptr++ = (unsigned char) (val & 0xFF);
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (sg_len && count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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if (host->pio.len == 0) {
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//IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
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IRQ_OFF(host, SD_CONFIG_NE);
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if (host->flags & HOST_F_STOP)
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SEND_STOP(host);
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tasklet_schedule(&host->data_task);
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}
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}
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/* static void au1xmmc_cmd_complete
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This is called when a command has been completed - grab the response
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and check for errors. Then start the data transfer if it is indicated.
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*/
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static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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{
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struct mmc_request *mrq = host->mrq;
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struct mmc_command *cmd;
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int trans;
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if (!host->mrq)
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return;
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cmd = mrq->cmd;
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cmd->error = MMC_ERR_NONE;
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136) {
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u32 r[4];
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int i;
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r[0] = au_readl(host->iobase + SD_RESP3);
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r[1] = au_readl(host->iobase + SD_RESP2);
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r[2] = au_readl(host->iobase + SD_RESP1);
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r[3] = au_readl(host->iobase + SD_RESP0);
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/* The CRC is omitted from the response, so really
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* we only got 120 bytes, but the engine expects
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* 128 bits, so we have to shift things up
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*/
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for(i = 0; i < 4; i++) {
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cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
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if (i != 3)
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cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
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}
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} else {
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/* Techincally, we should be getting all 48 bits of
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* the response (SD_RESP1 + SD_RESP2), but because
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* our response omits the CRC, our data ends up
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* being shifted 8 bits to the right. In this case,
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* that means that the OSR data starts at bit 31,
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* so we can just read RESP0 and return that
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*/
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cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
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}
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}
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/* Figure out errors */
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|
|
if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
|
|
cmd->error = MMC_ERR_BADCRC;
|
|
|
|
trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
|
|
|
|
if (!trans || cmd->error != MMC_ERR_NONE) {
|
|
|
|
IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
|
|
tasklet_schedule(&host->finish_task);
|
|
return;
|
|
}
|
|
|
|
host->status = HOST_S_DATA;
|
|
|
|
if (host->flags & HOST_F_DMA) {
|
|
u32 channel = DMA_CHANNEL(host);
|
|
|
|
/* Start the DMA as soon as the buffer gets something in it */
|
|
|
|
if (host->flags & HOST_F_RECV) {
|
|
u32 mask = SD_STATUS_DB | SD_STATUS_NE;
|
|
|
|
while((status & mask) != mask)
|
|
status = au_readl(HOST_STATUS(host));
|
|
}
|
|
|
|
au1xxx_dbdma_start(channel);
|
|
}
|
|
}
|
|
|
|
static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
|
|
{
|
|
|
|
unsigned int pbus = get_au1x00_speed();
|
|
unsigned int divisor;
|
|
u32 config;
|
|
|
|
/* From databook:
|
|
divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
|
|
*/
|
|
|
|
pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
|
|
pbus /= 2;
|
|
|
|
divisor = ((pbus / rate) / 2) - 1;
|
|
|
|
config = au_readl(HOST_CONFIG(host));
|
|
|
|
config &= ~(SD_CONFIG_DIV);
|
|
config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
|
|
|
|
au_writel(config, HOST_CONFIG(host));
|
|
au_sync();
|
|
}
|
|
|
|
static int
|
|
au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
|
|
{
|
|
|
|
int datalen = data->blocks * data->blksz;
|
|
|
|
if (dma != 0)
|
|
host->flags |= HOST_F_DMA;
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
host->flags |= HOST_F_RECV;
|
|
else
|
|
host->flags |= HOST_F_XMIT;
|
|
|
|
if (host->mrq->stop)
|
|
host->flags |= HOST_F_STOP;
|
|
|
|
host->dma.dir = DMA_BIDIRECTIONAL;
|
|
|
|
host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
|
|
data->sg_len, host->dma.dir);
|
|
|
|
if (host->dma.len == 0)
|
|
return MMC_ERR_TIMEOUT;
|
|
|
|
au_writel(data->blksz - 1, HOST_BLKSIZE(host));
|
|
|
|
if (host->flags & HOST_F_DMA) {
|
|
int i;
|
|
u32 channel = DMA_CHANNEL(host);
|
|
|
|
au1xxx_dbdma_stop(channel);
|
|
|
|
for(i = 0; i < host->dma.len; i++) {
|
|
u32 ret = 0, flags = DDMA_FLAGS_NOIE;
|
|
struct scatterlist *sg = &data->sg[i];
|
|
int sg_len = sg->length;
|
|
|
|
int len = (datalen > sg_len) ? sg_len : datalen;
|
|
|
|
if (i == host->dma.len - 1)
|
|
flags = DDMA_FLAGS_IE;
|
|
|
|
if (host->flags & HOST_F_XMIT){
|
|
ret = au1xxx_dbdma_put_source_flags(channel,
|
|
(void *) (page_address(sg->page) +
|
|
sg->offset),
|
|
len, flags);
|
|
}
|
|
else {
|
|
ret = au1xxx_dbdma_put_dest_flags(channel,
|
|
(void *) (page_address(sg->page) +
|
|
sg->offset),
|
|
len, flags);
|
|
}
|
|
|
|
if (!ret)
|
|
goto dataerr;
|
|
|
|
datalen -= len;
|
|
}
|
|
}
|
|
else {
|
|
host->pio.index = 0;
|
|
host->pio.offset = 0;
|
|
host->pio.len = datalen;
|
|
|
|
if (host->flags & HOST_F_XMIT)
|
|
IRQ_ON(host, SD_CONFIG_TH);
|
|
else
|
|
IRQ_ON(host, SD_CONFIG_NE);
|
|
//IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
|
|
}
|
|
|
|
return MMC_ERR_NONE;
|
|
|
|
dataerr:
|
|
dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
|
|
return MMC_ERR_TIMEOUT;
|
|
}
|
|
|
|
/* static void au1xmmc_request
|
|
This actually starts a command or data transaction
|
|
*/
|
|
|
|
static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
|
|
{
|
|
|
|
struct au1xmmc_host *host = mmc_priv(mmc);
|
|
unsigned int flags = 0;
|
|
int ret = MMC_ERR_NONE;
|
|
|
|
WARN_ON(irqs_disabled());
|
|
WARN_ON(host->status != HOST_S_IDLE);
|
|
|
|
host->mrq = mrq;
|
|
host->status = HOST_S_CMD;
|
|
|
|
bcsr->disk_leds &= ~(1 << 8);
|
|
|
|
if (mrq->data) {
|
|
FLUSH_FIFO(host);
|
|
flags = mrq->data->flags;
|
|
ret = au1xmmc_prepare_data(host, mrq->data);
|
|
}
|
|
|
|
if (ret == MMC_ERR_NONE)
|
|
ret = au1xmmc_send_command(host, 0, mrq->cmd, flags);
|
|
|
|
if (ret != MMC_ERR_NONE) {
|
|
mrq->cmd->error = ret;
|
|
au1xmmc_finish_request(host);
|
|
}
|
|
}
|
|
|
|
static void au1xmmc_reset_controller(struct au1xmmc_host *host)
|
|
{
|
|
|
|
/* Apply the clock */
|
|
au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
|
|
au_sync_delay(1);
|
|
|
|
au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
|
|
au_sync_delay(5);
|
|
|
|
au_writel(~0, HOST_STATUS(host));
|
|
au_sync();
|
|
|
|
au_writel(0, HOST_BLKSIZE(host));
|
|
au_writel(0x001fffff, HOST_TIMEOUT(host));
|
|
au_sync();
|
|
|
|
au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
|
|
au_sync_delay(1);
|
|
|
|
au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
/* Configure interrupts */
|
|
au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
|
|
au_sync();
|
|
}
|
|
|
|
|
|
static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
|
|
{
|
|
struct au1xmmc_host *host = mmc_priv(mmc);
|
|
|
|
if (ios->power_mode == MMC_POWER_OFF)
|
|
au1xmmc_set_power(host, 0);
|
|
else if (ios->power_mode == MMC_POWER_ON) {
|
|
au1xmmc_set_power(host, 1);
|
|
}
|
|
|
|
if (ios->clock && ios->clock != host->clock) {
|
|
au1xmmc_set_clock(host, ios->clock);
|
|
host->clock = ios->clock;
|
|
}
|
|
}
|
|
|
|
static void au1xmmc_dma_callback(int irq, void *dev_id)
|
|
{
|
|
struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
|
|
|
|
/* Avoid spurious interrupts */
|
|
|
|
if (!host->mrq)
|
|
return;
|
|
|
|
if (host->flags & HOST_F_STOP)
|
|
SEND_STOP(host);
|
|
|
|
tasklet_schedule(&host->data_task);
|
|
}
|
|
|
|
#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
|
|
#define STATUS_DATA_IN (SD_STATUS_NE)
|
|
#define STATUS_DATA_OUT (SD_STATUS_TH)
|
|
|
|
static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
|
|
{
|
|
|
|
u32 status;
|
|
int i, ret = 0;
|
|
|
|
disable_irq(AU1100_SD_IRQ);
|
|
|
|
for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
|
|
struct au1xmmc_host * host = au1xmmc_hosts[i];
|
|
u32 handled = 1;
|
|
|
|
status = au_readl(HOST_STATUS(host));
|
|
|
|
if (host->mrq && (status & STATUS_TIMEOUT)) {
|
|
if (status & SD_STATUS_RAT)
|
|
host->mrq->cmd->error = MMC_ERR_TIMEOUT;
|
|
|
|
else if (status & SD_STATUS_DT)
|
|
host->mrq->data->error = MMC_ERR_TIMEOUT;
|
|
|
|
/* In PIO mode, interrupts might still be enabled */
|
|
IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
|
|
|
|
//IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
|
|
tasklet_schedule(&host->finish_task);
|
|
}
|
|
#if 0
|
|
else if (status & SD_STATUS_DD) {
|
|
|
|
/* Sometimes we get a DD before a NE in PIO mode */
|
|
|
|
if (!(host->flags & HOST_F_DMA) &&
|
|
(status & SD_STATUS_NE))
|
|
au1xmmc_receive_pio(host);
|
|
else {
|
|
au1xmmc_data_complete(host, status);
|
|
//tasklet_schedule(&host->data_task);
|
|
}
|
|
}
|
|
#endif
|
|
else if (status & (SD_STATUS_CR)) {
|
|
if (host->status == HOST_S_CMD)
|
|
au1xmmc_cmd_complete(host,status);
|
|
}
|
|
else if (!(host->flags & HOST_F_DMA)) {
|
|
if ((host->flags & HOST_F_XMIT) &&
|
|
(status & STATUS_DATA_OUT))
|
|
au1xmmc_send_pio(host);
|
|
else if ((host->flags & HOST_F_RECV) &&
|
|
(status & STATUS_DATA_IN))
|
|
au1xmmc_receive_pio(host);
|
|
}
|
|
else if (status & 0x203FBC70) {
|
|
DBG("Unhandled status %8.8x\n", host->id, status);
|
|
handled = 0;
|
|
}
|
|
|
|
au_writel(status, HOST_STATUS(host));
|
|
au_sync();
|
|
|
|
ret |= handled;
|
|
}
|
|
|
|
enable_irq(AU1100_SD_IRQ);
|
|
return ret;
|
|
}
|
|
|
|
static void au1xmmc_poll_event(unsigned long arg)
|
|
{
|
|
struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
|
|
|
|
int card = au1xmmc_card_inserted(host);
|
|
int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
|
|
|
|
if (card != controller) {
|
|
host->flags &= ~HOST_F_ACTIVE;
|
|
if (card) host->flags |= HOST_F_ACTIVE;
|
|
mmc_detect_change(host->mmc, 0);
|
|
}
|
|
|
|
if (host->mrq != NULL) {
|
|
u32 status = au_readl(HOST_STATUS(host));
|
|
DBG("PENDING - %8.8x\n", host->id, status);
|
|
}
|
|
|
|
mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
|
|
}
|
|
|
|
static dbdev_tab_t au1xmmc_mem_dbdev =
|
|
{
|
|
DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
|
|
};
|
|
|
|
static void au1xmmc_init_dma(struct au1xmmc_host *host)
|
|
{
|
|
|
|
u32 rxchan, txchan;
|
|
|
|
int txid = au1xmmc_card_table[host->id].tx_devid;
|
|
int rxid = au1xmmc_card_table[host->id].rx_devid;
|
|
|
|
/* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
|
|
of 8 bits. And since devices are shared, we need to create
|
|
our own to avoid freaking out other devices
|
|
*/
|
|
|
|
int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
|
|
|
|
txchan = au1xxx_dbdma_chan_alloc(memid, txid,
|
|
au1xmmc_dma_callback, (void *) host);
|
|
|
|
rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
|
|
au1xmmc_dma_callback, (void *) host);
|
|
|
|
au1xxx_dbdma_set_devwidth(txchan, 8);
|
|
au1xxx_dbdma_set_devwidth(rxchan, 8);
|
|
|
|
au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
|
|
au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
|
|
|
|
host->tx_chan = txchan;
|
|
host->rx_chan = rxchan;
|
|
}
|
|
|
|
static const struct mmc_host_ops au1xmmc_ops = {
|
|
.request = au1xmmc_request,
|
|
.set_ios = au1xmmc_set_ios,
|
|
.get_ro = au1xmmc_card_readonly,
|
|
};
|
|
|
|
static int __devinit au1xmmc_probe(struct platform_device *pdev)
|
|
{
|
|
|
|
int i, ret = 0;
|
|
|
|
/* THe interrupt is shared among all controllers */
|
|
ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
|
|
|
|
if (ret) {
|
|
printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
|
|
AU1100_SD_IRQ, ret);
|
|
return -ENXIO;
|
|
}
|
|
|
|
disable_irq(AU1100_SD_IRQ);
|
|
|
|
for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
|
|
struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
|
|
struct au1xmmc_host *host = 0;
|
|
|
|
if (!mmc) {
|
|
printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
|
|
au1xmmc_hosts[i] = 0;
|
|
continue;
|
|
}
|
|
|
|
mmc->ops = &au1xmmc_ops;
|
|
|
|
mmc->f_min = 450000;
|
|
mmc->f_max = 24000000;
|
|
|
|
mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
|
|
mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
|
|
|
|
mmc->max_blk_size = 2048;
|
|
mmc->max_blk_count = 512;
|
|
|
|
mmc->ocr_avail = AU1XMMC_OCR;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
|
|
host->id = i;
|
|
host->iobase = au1xmmc_card_table[host->id].iobase;
|
|
host->clock = 0;
|
|
host->power_mode = MMC_POWER_OFF;
|
|
|
|
host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
|
|
host->status = HOST_S_IDLE;
|
|
|
|
init_timer(&host->timer);
|
|
|
|
host->timer.function = au1xmmc_poll_event;
|
|
host->timer.data = (unsigned long) host;
|
|
host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
|
|
|
|
tasklet_init(&host->data_task, au1xmmc_tasklet_data,
|
|
(unsigned long) host);
|
|
|
|
tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
|
|
(unsigned long) host);
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
if (dma != 0)
|
|
au1xmmc_init_dma(host);
|
|
|
|
au1xmmc_reset_controller(host);
|
|
|
|
mmc_add_host(mmc);
|
|
au1xmmc_hosts[i] = host;
|
|
|
|
add_timer(&host->timer);
|
|
|
|
printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
|
|
host->id, host->iobase, dma ? "dma" : "pio");
|
|
}
|
|
|
|
enable_irq(AU1100_SD_IRQ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit au1xmmc_remove(struct platform_device *pdev)
|
|
{
|
|
|
|
int i;
|
|
|
|
disable_irq(AU1100_SD_IRQ);
|
|
|
|
for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
|
|
struct au1xmmc_host *host = au1xmmc_hosts[i];
|
|
if (!host) continue;
|
|
|
|
tasklet_kill(&host->data_task);
|
|
tasklet_kill(&host->finish_task);
|
|
|
|
del_timer_sync(&host->timer);
|
|
au1xmmc_set_power(host, 0);
|
|
|
|
mmc_remove_host(host->mmc);
|
|
|
|
au1xxx_dbdma_chan_free(host->tx_chan);
|
|
au1xxx_dbdma_chan_free(host->rx_chan);
|
|
|
|
au_writel(0x0, HOST_ENABLE(host));
|
|
au_sync();
|
|
}
|
|
|
|
free_irq(AU1100_SD_IRQ, 0);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver au1xmmc_driver = {
|
|
.probe = au1xmmc_probe,
|
|
.remove = au1xmmc_remove,
|
|
.suspend = NULL,
|
|
.resume = NULL,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init au1xmmc_init(void)
|
|
{
|
|
return platform_driver_register(&au1xmmc_driver);
|
|
}
|
|
|
|
static void __exit au1xmmc_exit(void)
|
|
{
|
|
platform_driver_unregister(&au1xmmc_driver);
|
|
}
|
|
|
|
module_init(au1xmmc_init);
|
|
module_exit(au1xmmc_exit);
|
|
|
|
#ifdef MODULE
|
|
MODULE_AUTHOR("Advanced Micro Devices, Inc");
|
|
MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
|
|
MODULE_LICENSE("GPL");
|
|
#endif
|
|
|