forked from luck/tmp_suning_uos_patched
b3901d54dc
The patch adds support for thread creation and context switching. The context switching CPU specific code is introduced with the CPU support patch (part of the arch/arm64/mm/proc.S file). AArch64 supports ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable via the ID_AA64AFR0_EL1 register). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
160 lines
4.1 KiB
C
160 lines
4.1 KiB
C
/*
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* Based on arch/arm/mm/context.c
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*
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* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/cachetype.h>
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#define asid_bits(reg) \
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(((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
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#define ASID_FIRST_VERSION (1 << MAX_ASID_BITS)
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static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
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unsigned int cpu_last_asid = ASID_FIRST_VERSION;
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/*
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* We fork()ed a process, and we need a new context for the child to run in.
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*/
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.id = 0;
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raw_spin_lock_init(&mm->context.id_lock);
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}
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static void flush_context(void)
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{
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/* set the reserved TTBR0 before flushing the TLB */
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cpu_set_reserved_ttbr0();
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flush_tlb_all();
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if (icache_is_aivivt())
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__flush_icache_all();
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}
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#ifdef CONFIG_SMP
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static void set_mm_context(struct mm_struct *mm, unsigned int asid)
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{
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unsigned long flags;
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/*
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* Locking needed for multi-threaded applications where the same
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* mm->context.id could be set from different CPUs during the
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* broadcast. This function is also called via IPI so the
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* mm->context.id_lock has to be IRQ-safe.
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*/
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raw_spin_lock_irqsave(&mm->context.id_lock, flags);
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if (likely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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/*
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* Old version of ASID found. Set the new one and reset
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* mm_cpumask(mm).
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*/
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mm->context.id = asid;
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cpumask_clear(mm_cpumask(mm));
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}
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raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
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/*
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* Set the mm_cpumask(mm) bit for the current CPU.
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*/
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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/*
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* Reset the ASID on the current CPU. This function call is broadcast from the
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* CPU handling the ASID rollover and holding cpu_asid_lock.
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*/
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static void reset_context(void *info)
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{
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unsigned int asid;
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unsigned int cpu = smp_processor_id();
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struct mm_struct *mm = current->active_mm;
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smp_rmb();
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asid = cpu_last_asid + cpu;
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flush_context();
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set_mm_context(mm, asid);
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/* set the new ASID */
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cpu_switch_mm(mm->pgd, mm);
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}
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#else
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static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
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{
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mm->context.id = asid;
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cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
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}
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#endif
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void __new_context(struct mm_struct *mm)
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{
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unsigned int asid;
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unsigned int bits = asid_bits();
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raw_spin_lock(&cpu_asid_lock);
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#ifdef CONFIG_SMP
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/*
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* Check the ASID again, in case the change was broadcast from another
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* CPU before we acquired the lock.
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*/
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if (!unlikely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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raw_spin_unlock(&cpu_asid_lock);
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return;
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}
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#endif
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/*
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* At this point, it is guaranteed that the current mm (with an old
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* ASID) isn't active on any other CPU since the ASIDs are changed
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* simultaneously via IPI.
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*/
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asid = ++cpu_last_asid;
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/*
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* If we've used up all our ASIDs, we need to start a new version and
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* flush the TLB.
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*/
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if (unlikely((asid & ((1 << bits) - 1)) == 0)) {
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/* increment the ASID version */
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cpu_last_asid += (1 << MAX_ASID_BITS) - (1 << bits);
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if (cpu_last_asid == 0)
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cpu_last_asid = ASID_FIRST_VERSION;
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asid = cpu_last_asid + smp_processor_id();
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flush_context();
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#ifdef CONFIG_SMP
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smp_wmb();
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smp_call_function(reset_context, NULL, 1);
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#endif
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cpu_last_asid += NR_CPUS - 1;
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}
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set_mm_context(mm, asid);
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raw_spin_unlock(&cpu_asid_lock);
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}
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