forked from luck/tmp_suning_uos_patched
144b9c135b
eieio is only a store - store ordering. When used to order an unlock operation loads may leak out of the critical region. This is potentially buggy, one example is if a user wants to atomically read a couple of values. We can solve this with an lwsync which orders everything except store - load. I removed the (now unused) EIEIO_ON_SMP macros and the c versions isync_on_smp and eieio_on_smp now we dont use them. I also removed some old comments that were used to identify inline spinlocks in assembly, they dont make sense now our locks are out of line. Another interesting thing was that read_unlock was using an eieio even though the rest of the spinlock code had already been converted to use lwsync. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
409 lines
7.9 KiB
C
409 lines
7.9 KiB
C
#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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typedef struct { volatile int counter; } atomic_t;
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#ifdef __KERNEL__
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#include <asm/synch.h>
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#include <asm/asm-compat.h>
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static __inline__ void atomic_add(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_add\n\
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add %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_add_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ void atomic_sub(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_sub\n\
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subf %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_sub_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_dec_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns non-zero if @v was not @u, and zero otherwise.
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*/
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#define atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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for (;;) { \
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if (unlikely(c == (u))) \
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break; \
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old = atomic_cmpxchg((v), c, c + (a)); \
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if (likely(old == c)) \
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break; \
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c = old; \
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} \
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c != (u); \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#ifdef __powerpc64__
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typedef struct { volatile long counter; } atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic64_read(v) ((v)->counter)
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#define atomic64_set(v,i) (((v)->counter) = (i))
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static __inline__ void atomic64_add(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_add\n\
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add %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_add_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: ldarx %0,0,%2 # atomic64_add_return\n\
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add %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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static __inline__ void atomic64_sub(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_sub\n\
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subf %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: ldarx %0,0,%2 # atomic64_sub_return\n\
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subf %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic64_inc(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_inc\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_inc_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_inc_return\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%1 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic64_inc_and_test - increment and test
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* @v: pointer of type atomic64_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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static __inline__ void atomic64_dec(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_dec\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ long atomic64_dec_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_dec_return\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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LWSYNC_ON_SMP
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"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#endif /* __powerpc64__ */
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#include <asm-generic/atomic.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_ATOMIC_H_ */
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