forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* include/asm-v850/ma.h -- V850E/MA series of cpu chips
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_MA_H__
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#define __V850_MA_H__
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/* The MA series uses the V850E cpu core. */
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#include <asm/v850e.h>
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/* For <asm/entry.h> */
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/* We use on-chip RAM, for a few miscellaneous variables that must be
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accessible using a load instruction relative to R0. The amount
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varies between chip models, but there's always at least 4K, and it
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should always start at FFFFC000. */
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#define R0_RAM_ADDR 0xFFFFC000
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/* MA series UART details. */
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#define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
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/* This is a function that gets called before configuring the UART. */
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#define V850E_UART_PRE_CONFIGURE ma_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void ma_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* MA series timer C details. */
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#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
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/* MA series timer D details. */
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#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
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#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
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#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
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#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
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#define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
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/* Port 0 */
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/* Direct I/O. Bits 0-7 are pins P00-P07. */
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#define MA_PORT0_IO_ADDR 0xFFFFF400
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#define MA_PORT0_IO (*(volatile u8 *)MA_PORT0_IO_ADDR)
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/* Port mode (for direct I/O, 0 = output, 1 = input). */
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#define MA_PORT0_PM_ADDR 0xFFFFF420
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#define MA_PORT0_PM (*(volatile u8 *)MA_PORT0_PM_ADDR)
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/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
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#define MA_PORT0_PMC_ADDR 0xFFFFF440
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#define MA_PORT0_PMC (*(volatile u8 *)MA_PORT0_PMC_ADDR)
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/* Port function control (for P04-P07, 0 = IRQ, 1 = DMARQ). */
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#define MA_PORT0_PFC_ADDR 0xFFFFF460
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#define MA_PORT0_PFC (*(volatile u8 *)MA_PORT0_PFC_ADDR)
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/* Port 1 */
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/* Direct I/O. Bits 0-3 are pins P10-P13. */
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#define MA_PORT1_IO_ADDR 0xFFFFF402
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#define MA_PORT1_IO (*(volatile u8 *)MA_PORT1_IO_ADDR)
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/* Port mode (for direct I/O, 0 = output, 1 = input). */
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#define MA_PORT1_PM_ADDR 0xFFFFF420
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#define MA_PORT1_PM (*(volatile u8 *)MA_PORT1_PM_ADDR)
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/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
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#define MA_PORT1_PMC_ADDR 0xFFFFF442
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#define MA_PORT1_PMC (*(volatile u8 *)MA_PORT1_PMC_ADDR)
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/* Port 4 */
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/* Direct I/O. Bits 0-5 are pins P40-P45. */
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#define MA_PORT4_IO_ADDR 0xFFFFF408
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#define MA_PORT4_IO (*(volatile u8 *)MA_PORT4_IO_ADDR)
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/* Port mode (for direct I/O, 0 = output, 1 = input). */
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#define MA_PORT4_PM_ADDR 0xFFFFF428
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#define MA_PORT4_PM (*(volatile u8 *)MA_PORT4_PM_ADDR)
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/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
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#define MA_PORT4_PMC_ADDR 0xFFFFF448
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#define MA_PORT4_PMC (*(volatile u8 *)MA_PORT4_PMC_ADDR)
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/* Port function control (for serial interfaces, 0 = CSI, 1 = UART). */
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#define MA_PORT4_PFC_ADDR 0xFFFFF468
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#define MA_PORT4_PFC (*(volatile u8 *)MA_PORT4_PFC_ADDR)
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#ifndef __ASSEMBLY__
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/* Initialize MA chip interrupts. */
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extern void ma_init_irqs (void);
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#endif /* !__ASSEMBLY__ */
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#endif /* __V850_MA_H__ */
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