Masahiro Yamada e6914365fd reset: uniphier: fix USB clock line for LD20 ... For LD20, the bit 5 of the offset 0x200c turned out to be a USB3 reset. The hardware document says it is the GIO reset despite LD20 has no GIO bus, confusingly. Also, fix confusing comments for PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>		2018-04-27 11:51:12 +02:00
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hisilicon
sti
tegra
core.c	reset: modify the way reset lookup works for board files	2018-03-27 10:39:47 +02:00
Kconfig	reset: stm32mp1: Enable stm32mp1 reset driver	2018-03-27 10:44:04 +02:00
Makefile	reset: stm32mp1: Enable stm32mp1 reset driver	2018-03-27 10:44:04 +02:00
reset-a10sr.c
reset-ath79.c
reset-axs10x.c
reset-berlin.c
reset-hsdk.c
reset-imx7.c
reset-lantiq.c
reset-lpc18xx.c
reset-meson.c	reset: meson: enable level reset support on Meson8b	2018-02-16 15:32:09 +01:00
reset-oxnas.c
reset-pistachio.c
reset-simple.c	reset: simple: Enable for ASPEED systems	2018-02-20 17:42:29 +01:00
reset-simple.h
reset-stm32mp1.c	reset: stm32mp1: Enable stm32mp1 reset driver	2018-03-27 10:44:04 +02:00
reset-sunxi.c
reset-ti-sci.c
reset-ti-syscon.c
reset-uniphier.c	reset: uniphier: fix USB clock line for LD20	2018-04-27 11:51:12 +02:00
reset-zynq.c