kernel_optimize_test/arch/riscv/kernel
Alan Kao 178e9fc47a
perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles.  Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.

riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec.  Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes.  Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.

Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-06-04 14:02:01 -07:00
..
vdso RISC-V: build vdso-dummy.o with -no-pie 2018-04-24 10:54:46 -07:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
asm-offsets.c RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
cacheinfo.c
cpu.c
cpufeature.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
entry.S RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
ftrace.c riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support 2018-04-02 19:59:13 -07:00
head.S Rename sbi_save to parse_dtb to improve code readability 2018-02-20 10:56:26 -08:00
irq.c RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
Makefile perf: riscv: preliminary RISC-V support 2018-06-04 14:02:01 -07:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S riscv/ftrace: Add dynamic function tracer support 2018-04-02 19:59:12 -07:00
module-sections.c RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
module.c RISC-V: Support SUB32 relocation type in kernel module 2018-04-02 20:00:55 -07:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_event.c perf: riscv: preliminary RISC-V support 2018-06-04 14:02:01 -07:00
process.c Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs 2018-01-31 19:18:12 -08:00
ptrace.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
reset.c
riscv_ksyms.c RISC-V: Export some expected symbols for modules 2017-11-30 10:01:10 -08:00
setup.c Rename sbi_save to parse_dtb to improve code readability 2018-02-20 10:56:26 -08:00
signal.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
smp.c RISC-V: Fixes for clean allmodconfig build 2017-12-01 13:31:31 -08:00
smpboot.c
stacktrace.c riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support 2018-04-02 19:59:13 -07:00
sys_riscv.c mm: add ksys_mmap_pgoff() helper; remove in-kernel calls to sys_mmap_pgoff() 2018-04-02 20:16:11 +02:00
syscall_table.c RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
time.c
traps.c
vdso.c riscv: remove redundant unlikely() 2018-01-30 19:12:06 -08:00
vmlinux.lds.S RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00