forked from luck/tmp_suning_uos_patched
e81b6abebc
Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks to run. This driver handle those clocks. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* Atmel (Multi-port DDR-)SDRAM Controller driver
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*
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* Copyright (C) 2014 Atmel
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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struct at91_ramc_caps {
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bool has_ddrck;
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bool has_mpddr_clk;
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};
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static const struct at91_ramc_caps at91rm9200_caps = { };
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static const struct at91_ramc_caps at91sam9g45_caps = {
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.has_ddrck = 1,
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.has_mpddr_clk = 0,
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};
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static const struct at91_ramc_caps sama5d3_caps = {
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.has_ddrck = 1,
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.has_mpddr_clk = 1,
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};
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static const struct of_device_id atmel_ramc_of_match[] = {
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{ .compatible = "atmel,at91rm9200-sdramc", .data = &at91rm9200_caps, },
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{ .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, },
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{ .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, },
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{ .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, },
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{},
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};
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MODULE_DEVICE_TABLE(of, atmel_ramc_of_match);
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static int atmel_ramc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct at91_ramc_caps *caps;
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struct clk *clk;
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match = of_match_device(atmel_ramc_of_match, &pdev->dev);
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caps = match->data;
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if (caps->has_ddrck) {
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clk = devm_clk_get(&pdev->dev, "ddrck");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_prepare_enable(clk);
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}
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if (caps->has_mpddr_clk) {
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clk = devm_clk_get(&pdev->dev, "mpddr");
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if (IS_ERR(clk)) {
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pr_err("AT91 RAMC: couldn't get mpddr clock\n");
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return PTR_ERR(clk);
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}
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clk_prepare_enable(clk);
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}
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return 0;
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}
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static struct platform_driver atmel_ramc_driver = {
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.probe = atmel_ramc_probe,
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.driver = {
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.name = "atmel-ramc",
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.owner = THIS_MODULE,
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.of_match_table = atmel_ramc_of_match,
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},
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};
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static int __init atmel_ramc_init(void)
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{
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return platform_driver_register(&atmel_ramc_driver);
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}
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module_init(atmel_ramc_init);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
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MODULE_DESCRIPTION("Atmel (Multi-port DDR-)SDRAM Controller");
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