forked from luck/tmp_suning_uos_patched
cf0d19fb30
add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them. Add same to platform probe code.
This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.
also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd4473: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
368 lines
8.1 KiB
Plaintext
368 lines
8.1 KiB
Plaintext
/*
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* MPC8378E MDS Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,mpc8378emds";
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compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8378@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; // 512MB at 0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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// booting from NOR flash
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ranges = <0 0x0 0xfe000000 0x02000000
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1 0x0 0xf8000000 0x00008000
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3 0x0 0xe0600000 0x00008000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0 0x0 0x2000000>;
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bank-width = <2>;
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device-width = <1>;
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u-boot@0 {
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reg = <0x0 0x100000>;
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read-only;
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};
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fs@100000 {
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reg = <0x100000 0x800000>;
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};
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kernel@1d00000 {
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reg = <0x1d00000 0x200000>;
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};
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dtb@1f00000 {
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reg = <0x1f00000 0x100000>;
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};
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};
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bcsr@1,0 {
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reg = <1 0x0 0x8000>;
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compatible = "fsl,mpc837xmds-bcsr";
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};
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nand@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8378-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <3 0x0 0x8000>;
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u-boot@0 {
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reg = <0x0 0x100000>;
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read-only;
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};
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kernel@100000 {
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reg = <0x100000 0x300000>;
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};
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fs@400000 {
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reg = <0x400000 0x1c00000>;
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};
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};
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <15 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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spi@7000 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy2: ethernet-phy@2 {
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interrupt-parent = <&ipic>;
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interrupts = <17 0x8>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&ipic>;
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interrupts = <18 0x8>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = <&ipic>;
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phy-handle = <&phy2>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 0x8 36 0x8 37 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = <&ipic>;
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phy-handle = <&phy3>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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sdhc@2e000 {
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model = "eSDHC";
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compatible = "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <42 0x8>;
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interrupt-parent = <&ipic>;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: pic@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <0>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0x0 0x0 0x1 &ipic 20 0x8
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0x8800 0x0 0x0 0x2 &ipic 21 0x8
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0x8800 0x0 0x0 0x3 &ipic 22 0x8
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0x8800 0x0 0x0 0x4 &ipic 23 0x8
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/* IDSEL 0x12 */
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0x9000 0x0 0x0 0x1 &ipic 22 0x8
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0x9000 0x0 0x0 0x2 &ipic 23 0x8
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0x9000 0x0 0x0 0x3 &ipic 20 0x8
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0x9000 0x0 0x0 0x4 &ipic 21 0x8
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/* IDSEL 0x13 */
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0x9800 0x0 0x0 0x1 &ipic 23 0x8
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0x9800 0x0 0x0 0x2 &ipic 20 0x8
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0x9800 0x0 0x0 0x3 &ipic 21 0x8
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0x9800 0x0 0x0 0x4 &ipic 22 0x8
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &ipic 20 0x8
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0xa800 0x0 0x0 0x2 &ipic 21 0x8
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0xa800 0x0 0x0 0x3 &ipic 22 0x8
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0xa800 0x0 0x0 0x4 &ipic 23 0x8
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/* IDSEL 0x16 */
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0xb000 0x0 0x0 0x1 &ipic 23 0x8
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0xb000 0x0 0x0 0x2 &ipic 20 0x8
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0xb000 0x0 0x0 0x3 &ipic 21 0x8
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0xb000 0x0 0x0 0x4 &ipic 22 0x8
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/* IDSEL 0x17 */
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0xb800 0x0 0x0 0x1 &ipic 22 0x8
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0xb800 0x0 0x0 0x2 &ipic 23 0x8
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0xb800 0x0 0x0 0x3 &ipic 20 0x8
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0xb800 0x0 0x0 0x4 &ipic 21 0x8
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/* IDSEL 0x18 */
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0xc000 0x0 0x0 0x1 &ipic 21 0x8
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0xc000 0x0 0x0 0x2 &ipic 22 0x8
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0xc000 0x0 0x0 0x3 &ipic 23 0x8
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0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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