Vipul Kumar Samar d4f513ff12 Clk: SPEAr1340: Update sys clock parent array ... sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>		2012-07-18 10:04:53 +05:30
..
mxs
spear	Clk: SPEAr1340: Update sys clock parent array	2012-07-18 10:04:53 +05:30
clk-divider.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-gate.c
clk-mux.c
clk.c
clkdev.c
Kconfig
Makefile