forked from luck/tmp_suning_uos_patched
88278ca27a
This patch removes the CVS keywords that weren't updated for a long time from comments. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* turbosparc.h: Defines specific to the TurboSparc module.
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* This is SRMMU stuff.
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*
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* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#ifndef _SPARC_TURBOSPARC_H
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#define _SPARC_TURBOSPARC_H
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#include <asm/asi.h>
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#include <asm/pgtsrmmu.h>
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/* Bits in the SRMMU control register for TurboSparc modules.
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*
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* -------------------------------------------------------------------
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* |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
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* -------------------------------------------------------------------
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* 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
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*
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* BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
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*
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* This indicates whether the TurboSparc is in boot-mode or not.
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*
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* IC: Instruction Cache -- 0 = off, 1 = on
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* DC: Data Cache -- 0 = off, 1 = 0n
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*
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* These bits enable the on-cpu TurboSparc split I/D caches.
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*
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* ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
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* NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
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* ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
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*
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*/
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#define TURBOSPARC_MMUENABLE 0x00000001
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#define TURBOSPARC_NOFAULT 0x00000002
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#define TURBOSPARC_ICSNOOP 0x00000004
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#define TURBOSPARC_PSO 0x00000080
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#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
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#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
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#define TURBOSPARC_BMODE 0x00004000
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#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
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#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
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/* Bits in the CPU configuration register for TurboSparc modules.
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*
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* -------------------------------------------------------
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* |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
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* -------------------------------------------------------
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* 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
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*
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*/
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#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
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#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
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#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
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#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
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#ifndef __ASSEMBLY__
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/* Bits [13:5] select one of 512 instruction cache tags */
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static inline void turbosparc_inv_insn_tag(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_TXTC_TAG)
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: "memory");
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}
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/* Bits [13:5] select one of 512 data cache tags */
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static inline void turbosparc_inv_data_tag(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_DATAC_TAG)
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: "memory");
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}
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static inline void turbosparc_flush_icache(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x4000; addr += 0x20)
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turbosparc_inv_insn_tag(addr);
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}
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static inline void turbosparc_flush_dcache(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x4000; addr += 0x20)
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turbosparc_inv_data_tag(addr);
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}
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static inline void turbosparc_idflash_clear(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x4000; addr += 0x20) {
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turbosparc_inv_insn_tag(addr);
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turbosparc_inv_data_tag(addr);
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}
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}
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static inline void turbosparc_set_ccreg(unsigned long regval)
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{
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__asm__ __volatile__("sta %0, [%1] %2\n\t"
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: /* no outputs */
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: "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
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: "memory");
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}
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static inline unsigned long turbosparc_get_ccreg(void)
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{
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unsigned long regval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t"
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: "=r" (regval)
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: "r" (0x600), "i" (ASI_M_MMUREGS));
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return regval;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !(_SPARC_TURBOSPARC_H) */
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