forked from luck/tmp_suning_uos_patched
1acf1ca7e9
The modpost uses a whitelist for commonly used suffix on checking the
section mismatch. Adding "_ops" suffix to op_modex_xxx get rid of
this modpost warning.
WARNING: arch/mips/oprofile/oprofile.o - Section mismatch: reference to .init.text: from .data after 'op_model_mipsxx' (at offset 0x528)
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 by Ralf Baechle
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*/
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#include <linux/init.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include "op_impl.h"
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#define RM9K_COUNTER1_EVENT(event) ((event) << 0)
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#define RM9K_COUNTER1_SUPERVISOR (1ULL << 7)
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#define RM9K_COUNTER1_KERNEL (1ULL << 8)
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#define RM9K_COUNTER1_USER (1ULL << 9)
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#define RM9K_COUNTER1_ENABLE (1ULL << 10)
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#define RM9K_COUNTER1_OVERFLOW (1ULL << 15)
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#define RM9K_COUNTER2_EVENT(event) ((event) << 16)
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#define RM9K_COUNTER2_SUPERVISOR (1ULL << 23)
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#define RM9K_COUNTER2_KERNEL (1ULL << 24)
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#define RM9K_COUNTER2_USER (1ULL << 25)
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#define RM9K_COUNTER2_ENABLE (1ULL << 26)
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#define RM9K_COUNTER2_OVERFLOW (1ULL << 31)
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extern unsigned int rm9000_perfcount_irq;
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static struct rm9k_register_config {
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unsigned int control;
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unsigned int reset_counter1;
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unsigned int reset_counter2;
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} reg;
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/* Compute all of the registers in preparation for enabling profiling. */
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static void rm9000_reg_setup(struct op_counter_config *ctr)
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{
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unsigned int control = 0;
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/* Compute the performance counter control word. */
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/* For now count kernel and user mode */
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if (ctr[0].enabled)
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control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
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RM9K_COUNTER1_KERNEL |
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RM9K_COUNTER1_USER |
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RM9K_COUNTER1_ENABLE;
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if (ctr[1].enabled)
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control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
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RM9K_COUNTER2_KERNEL |
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RM9K_COUNTER2_USER |
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RM9K_COUNTER2_ENABLE;
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reg.control = control;
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reg.reset_counter1 = 0x80000000 - ctr[0].count;
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reg.reset_counter2 = 0x80000000 - ctr[1].count;
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void rm9000_cpu_setup (void *args)
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{
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uint64_t perfcount;
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perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
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write_c0_perfcount(perfcount);
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}
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static void rm9000_cpu_start(void *args)
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{
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/* Start all counters on current CPU */
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write_c0_perfcontrol(reg.control);
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}
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static void rm9000_cpu_stop(void *args)
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{
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/* Stop all counters on current CPU */
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write_c0_perfcontrol(0);
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}
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static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id,
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struct pt_regs *regs)
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{
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unsigned int control = read_c0_perfcontrol();
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uint32_t counter1, counter2;
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uint64_t counters;
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/*
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* RM9000 combines two 32-bit performance counters into a single
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* 64-bit coprocessor zero register. To avoid a race updating the
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* registers we need to stop the counters while we're messing with
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* them ...
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*/
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write_c0_perfcontrol(0);
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counters = read_c0_perfcount();
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counter1 = counters;
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counter2 = counters >> 32;
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if (control & RM9K_COUNTER1_OVERFLOW) {
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oprofile_add_sample(regs, 0);
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counter1 = reg.reset_counter1;
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}
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if (control & RM9K_COUNTER2_OVERFLOW) {
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oprofile_add_sample(regs, 1);
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counter2 = reg.reset_counter2;
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}
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counters = ((uint64_t)counter2 << 32) | counter1;
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write_c0_perfcount(counters);
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write_c0_perfcontrol(reg.control);
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return IRQ_HANDLED;
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}
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static int __init rm9000_init(void)
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{
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return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
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0, "Perfcounter", NULL);
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}
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static void rm9000_exit(void)
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{
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free_irq(rm9000_perfcount_irq, NULL);
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}
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struct op_mips_model op_model_rm9000_ops = {
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.reg_setup = rm9000_reg_setup,
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.cpu_setup = rm9000_cpu_setup,
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.init = rm9000_init,
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.exit = rm9000_exit,
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.cpu_start = rm9000_cpu_start,
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.cpu_stop = rm9000_cpu_stop,
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.cpu_type = "mips/rm9000",
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.num_counters = 2
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};
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