forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
939 lines
22 KiB
C
939 lines
22 KiB
C
/*
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* x86 SMP booting functions
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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* Copyright 2001 Andi Kleen, SuSE Labs.
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*
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* Much of the core SMP work is based on previous work by Thomas Radke, to
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* whom a great many thanks are extended.
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*
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* Thanks to Intel for making available several different Pentium,
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* Pentium Pro and Pentium-II/Xeon MP machines.
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* Original development of Linux SMP code supported by Caldera.
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*
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* Fixes
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* Felix Koop : NR_CPUS used properly
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* Jose Renau : Handle single CPU case.
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* Alan Cox : By repeated request 8) - Total BogoMIP report.
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* Greg Wright : Fix for kernel stacks panic.
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* Erich Boleyn : MP v1.4 and additional changes.
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* Matthias Sattler : Changes for 2.1 kernel map.
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* Michel Lespinasse : Changes for 2.1 kernel map.
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* Michael Chastain : Change trampoline.S to gnu as.
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* Alan Cox : Dumb bug: 'B' step PPro's are fine
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* Ingo Molnar : Added APIC timers, based on code
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* from Jose Renau
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* Ingo Molnar : various cleanups and rewrites
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* Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs
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* Andi Kleen : Changed for SMP boot into long mode.
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* Rusty Russell : Hacked into shape for new "hotplug" boot process.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/kernel_stat.h>
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#include <linux/smp_lock.h>
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/thread_info.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mtrr.h>
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#include <asm/pgalloc.h>
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#include <asm/desc.h>
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#include <asm/kdebug.h>
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#include <asm/tlbflush.h>
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#include <asm/proto.h>
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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/* Package ID of each logical CPU */
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u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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EXPORT_SYMBOL(phys_proc_id);
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/* Bitmask of currently online CPUs */
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cpumask_t cpu_online_map;
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cpumask_t cpu_callin_map;
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cpumask_t cpu_callout_map;
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static cpumask_t smp_commenced_mask;
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/* Per CPU bogomips and other parameters */
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struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
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cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
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/*
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* Trampoline 80x86 program as an array.
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*/
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extern unsigned char trampoline_data [];
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extern unsigned char trampoline_end [];
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/*
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* Currently trivial. Write the real->protected mode
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* bootstrap into the page concerned. The caller
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* has made sure it's suitably aligned.
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*/
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static unsigned long __init setup_trampoline(void)
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{
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void *tramp = __va(SMP_TRAMPOLINE_BASE);
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memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
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return virt_to_phys(tramp);
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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static void __init smp_store_cpu_info(int id)
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{
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struct cpuinfo_x86 *c = cpu_data + id;
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*c = boot_cpu_data;
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identify_cpu(c);
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}
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/*
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* TSC synchronization.
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*
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* We first check whether all CPUs have their TSC's synchronized,
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* then we print a warning if not, and always resync.
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*/
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static atomic_t tsc_start_flag = ATOMIC_INIT(0);
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static atomic_t tsc_count_start = ATOMIC_INIT(0);
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static atomic_t tsc_count_stop = ATOMIC_INIT(0);
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static unsigned long long tsc_values[NR_CPUS];
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#define NR_LOOPS 5
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extern unsigned int fast_gettimeoffset_quotient;
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static void __init synchronize_tsc_bp (void)
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{
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int i;
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unsigned long long t0;
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unsigned long long sum, avg;
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long long delta;
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long one_usec;
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int buggy = 0;
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printk(KERN_INFO "checking TSC synchronization across %u CPUs: ",num_booting_cpus());
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one_usec = cpu_khz;
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atomic_set(&tsc_start_flag, 1);
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wmb();
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/*
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* We loop a few times to get a primed instruction cache,
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* then the last pass is more or less synchronized and
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* the BP and APs set their cycle counters to zero all at
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* once. This reduces the chance of having random offsets
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* between the processors, and guarantees that the maximum
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* delay between the cycle counters is never bigger than
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* the latency of information-passing (cachelines) between
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* two CPUs.
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*/
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for (i = 0; i < NR_LOOPS; i++) {
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/*
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* all APs synchronize but they loop on '== num_cpus'
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*/
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while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) mb();
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atomic_set(&tsc_count_stop, 0);
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wmb();
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/*
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* this lets the APs save their current TSC:
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*/
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atomic_inc(&tsc_count_start);
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sync_core();
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rdtscll(tsc_values[smp_processor_id()]);
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/*
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* We clear the TSC in the last loop:
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*/
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if (i == NR_LOOPS-1)
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write_tsc(0, 0);
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/*
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* Wait for all APs to leave the synchronization point:
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*/
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while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) mb();
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atomic_set(&tsc_count_start, 0);
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wmb();
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atomic_inc(&tsc_count_stop);
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}
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sum = 0;
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for (i = 0; i < NR_CPUS; i++) {
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if (cpu_isset(i, cpu_callout_map)) {
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t0 = tsc_values[i];
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sum += t0;
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}
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}
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avg = sum / num_booting_cpus();
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sum = 0;
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for (i = 0; i < NR_CPUS; i++) {
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if (!cpu_isset(i, cpu_callout_map))
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continue;
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delta = tsc_values[i] - avg;
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if (delta < 0)
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delta = -delta;
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/*
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* We report bigger than 2 microseconds clock differences.
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*/
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if (delta > 2*one_usec) {
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long realdelta;
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if (!buggy) {
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buggy = 1;
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printk("\n");
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}
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realdelta = delta / one_usec;
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if (tsc_values[i] < avg)
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realdelta = -realdelta;
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printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
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i, realdelta);
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}
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sum += delta;
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}
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if (!buggy)
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printk("passed.\n");
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}
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static void __init synchronize_tsc_ap (void)
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{
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int i;
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/*
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* Not every cpu is online at the time
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* this gets called, so we first wait for the BP to
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* finish SMP initialization:
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*/
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while (!atomic_read(&tsc_start_flag)) mb();
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for (i = 0; i < NR_LOOPS; i++) {
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atomic_inc(&tsc_count_start);
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while (atomic_read(&tsc_count_start) != num_booting_cpus()) mb();
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sync_core();
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rdtscll(tsc_values[smp_processor_id()]);
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if (i == NR_LOOPS-1)
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write_tsc(0, 0);
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atomic_inc(&tsc_count_stop);
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while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
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}
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}
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#undef NR_LOOPS
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static atomic_t init_deasserted;
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static void __init smp_callin(void)
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{
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int cpuid, phys_id;
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unsigned long timeout;
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/*
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* If waken up by an INIT in an 82489DX configuration
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* we may get here before an INIT-deassert IPI reaches
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* our local APIC. We have to wait for the IPI or we'll
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* lock up on an APIC access.
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*/
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while (!atomic_read(&init_deasserted));
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/*
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* (This works even if the APIC is not enabled.)
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*/
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phys_id = GET_APIC_ID(apic_read(APIC_ID));
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cpuid = smp_processor_id();
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if (cpu_isset(cpuid, cpu_callin_map)) {
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panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
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phys_id, cpuid);
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}
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Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
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/*
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* STARTUP IPIs are fragile beasts as they might sometimes
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* trigger some glue motherboard logic. Complete APIC bus
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* silence for 1 second, this overestimates the time the
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* boot CPU is spending to send the up to 2 STARTUP IPIs
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* by a factor of two. This should be enough.
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*/
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/*
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* Waiting 2s total for startup (udelay is not yet working)
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*/
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timeout = jiffies + 2*HZ;
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while (time_before(jiffies, timeout)) {
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/*
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* Has the boot CPU finished it's STARTUP sequence?
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*/
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if (cpu_isset(cpuid, cpu_callout_map))
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break;
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rep_nop();
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}
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if (!time_before(jiffies, timeout)) {
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panic("smp_callin: CPU%d started up but did not get a callout!\n",
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cpuid);
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}
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/*
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* the boot CPU has finished the init stage and is spinning
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* on callin_map until we finish. We are free to set up this
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* CPU, first the APIC. (this is probably redundant on most
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* boards)
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*/
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Dprintk("CALLIN, before setup_local_APIC().\n");
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setup_local_APIC();
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local_irq_enable();
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/*
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* Get our bogomips.
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*/
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calibrate_delay();
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Dprintk("Stack at about %p\n",&cpuid);
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disable_APIC_timer();
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/*
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* Save our processor parameters
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*/
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smp_store_cpu_info(cpuid);
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local_irq_disable();
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/*
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* Allow the master to continue.
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*/
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cpu_set(cpuid, cpu_callin_map);
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/*
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* Synchronize the TSC with the BP
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*/
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if (cpu_has_tsc)
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synchronize_tsc_ap();
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}
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static int cpucount;
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/*
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* Activate a secondary processor.
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*/
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void __init start_secondary(void)
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{
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/*
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* Dont put anything before smp_callin(), SMP
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* booting is too fragile that we want to limit the
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* things done here to the most necessary things.
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*/
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cpu_init();
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smp_callin();
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/* otherwise gcc will move up the smp_processor_id before the cpu_init */
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barrier();
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Dprintk("cpu %d: waiting for commence\n", smp_processor_id());
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while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
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rep_nop();
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Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
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setup_secondary_APIC_clock();
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Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0(NULL);
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enable_8259A_irq(0);
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}
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enable_APIC_timer();
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/*
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* low-memory mappings have been cleared, flush them from
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* the local TLBs too.
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*/
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local_flush_tlb();
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Dprintk("cpu %d eSetting cpu_online_map\n", smp_processor_id());
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cpu_set(smp_processor_id(), cpu_online_map);
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wmb();
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cpu_idle();
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}
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extern volatile unsigned long init_rsp;
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extern void (*initial_code)(void);
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#if APIC_DEBUG
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static inline void inquire_remote_apic(int apicid)
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{
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unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
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char *names[] = { "ID", "VERSION", "SPIV" };
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int timeout, status;
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printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
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for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
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printk("... APIC #%d %s: ", apicid, names[i]);
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/*
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* Wait for idle.
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*/
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apic_wait_icr_idle();
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
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timeout = 0;
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do {
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udelay(100);
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status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
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} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
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switch (status) {
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case APIC_ICR_RR_VALID:
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status = apic_read(APIC_RRR);
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printk("%08x\n", status);
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break;
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default:
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printk("failed\n");
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}
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}
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}
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#endif
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static int __init wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
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{
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unsigned long send_status = 0, accept_status = 0;
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int maxlvt, timeout, num_starts, j;
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Dprintk("Asserting INIT.\n");
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/*
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* Turn INIT on target chip
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*/
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
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/*
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* Send IPI
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*/
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
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| APIC_DM_INIT);
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Dprintk("Waiting for send to finish...\n");
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timeout = 0;
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do {
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Dprintk("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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mdelay(10);
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Dprintk("Deasserting INIT.\n");
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/* Target chip */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
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|
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/* Send IPI */
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apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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Dprintk("Waiting for send to finish...\n");
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timeout = 0;
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do {
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Dprintk("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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atomic_set(&init_deasserted, 1);
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/*
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* Should we send STARTUP IPIs ?
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*
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* Determine this based on the APIC version.
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* If we don't have an integrated APIC, don't send the STARTUP IPIs.
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*/
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if (APIC_INTEGRATED(apic_version[phys_apicid]))
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num_starts = 2;
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else
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num_starts = 0;
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/*
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* Run STARTUP IPI loop.
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*/
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Dprintk("#startup loops: %d.\n", num_starts);
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maxlvt = get_maxlvt();
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for (j = 1; j <= num_starts; j++) {
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Dprintk("Sending STARTUP #%d.\n",j);
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apic_read_around(APIC_SPIV);
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apic_write(APIC_ESR, 0);
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apic_read(APIC_ESR);
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Dprintk("After apic_write.\n");
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|
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/*
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* STARTUP IPI
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*/
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/* Target chip */
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apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
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|
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/* Boot on the stack */
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/* Kick the second */
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apic_write_around(APIC_ICR, APIC_DM_STARTUP
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| (start_rip >> 12));
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|
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/*
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* Give the other CPU some time to accept the IPI.
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*/
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udelay(300);
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Dprintk("Startup point 1.\n");
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Dprintk("Waiting for send to finish...\n");
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timeout = 0;
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do {
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Dprintk("+");
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udelay(100);
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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} while (send_status && (timeout++ < 1000));
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|
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/*
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* Give the other CPU some time to accept the IPI.
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*/
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udelay(200);
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/*
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* Due to the Pentium erratum 3AP.
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|
*/
|
|
if (maxlvt > 3) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
}
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
if (send_status || accept_status)
|
|
break;
|
|
}
|
|
Dprintk("After Startup.\n");
|
|
|
|
if (send_status)
|
|
printk(KERN_ERR "APIC never delivered???\n");
|
|
if (accept_status)
|
|
printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
|
|
static void __init do_boot_cpu (int apicid)
|
|
{
|
|
struct task_struct *idle;
|
|
unsigned long boot_error;
|
|
int timeout, cpu;
|
|
unsigned long start_rip;
|
|
|
|
cpu = ++cpucount;
|
|
/*
|
|
* We can't use kernel_thread since we must avoid to
|
|
* reschedule the child.
|
|
*/
|
|
idle = fork_idle(cpu);
|
|
if (IS_ERR(idle))
|
|
panic("failed fork for CPU %d", cpu);
|
|
x86_cpu_to_apicid[cpu] = apicid;
|
|
|
|
cpu_pda[cpu].pcurrent = idle;
|
|
|
|
start_rip = setup_trampoline();
|
|
|
|
init_rsp = idle->thread.rsp;
|
|
per_cpu(init_tss,cpu).rsp0 = init_rsp;
|
|
initial_code = start_secondary;
|
|
clear_ti_thread_flag(idle->thread_info, TIF_FORK);
|
|
|
|
printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
|
|
start_rip, init_rsp);
|
|
|
|
/*
|
|
* This grunge runs the startup process for
|
|
* the targeted processor.
|
|
*/
|
|
|
|
atomic_set(&init_deasserted, 0);
|
|
|
|
Dprintk("Setting warm reset code and vector.\n");
|
|
|
|
CMOS_WRITE(0xa, 0xf);
|
|
local_flush_tlb();
|
|
Dprintk("1.\n");
|
|
*((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
|
|
Dprintk("2.\n");
|
|
*((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
|
|
Dprintk("3.\n");
|
|
|
|
/*
|
|
* Be paranoid about clearing APIC errors.
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[apicid])) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
|
|
/*
|
|
* Status is now clean
|
|
*/
|
|
boot_error = 0;
|
|
|
|
/*
|
|
* Starting actual IPI sequence...
|
|
*/
|
|
boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
|
|
|
|
if (!boot_error) {
|
|
/*
|
|
* allow APs to start initializing.
|
|
*/
|
|
Dprintk("Before Callout %d.\n", cpu);
|
|
cpu_set(cpu, cpu_callout_map);
|
|
Dprintk("After Callout %d.\n", cpu);
|
|
|
|
/*
|
|
* Wait 5s total for a response
|
|
*/
|
|
for (timeout = 0; timeout < 50000; timeout++) {
|
|
if (cpu_isset(cpu, cpu_callin_map))
|
|
break; /* It has booted */
|
|
udelay(100);
|
|
}
|
|
|
|
if (cpu_isset(cpu, cpu_callin_map)) {
|
|
/* number CPUs logically, starting from 1 (BSP is 0) */
|
|
Dprintk("OK.\n");
|
|
print_cpu_info(&cpu_data[cpu]);
|
|
Dprintk("CPU has booted.\n");
|
|
} else {
|
|
boot_error = 1;
|
|
if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
|
|
== 0xA5)
|
|
/* trampoline started but...? */
|
|
printk("Stuck ??\n");
|
|
else
|
|
/* trampoline code not run */
|
|
printk("Not responding.\n");
|
|
#if APIC_DEBUG
|
|
inquire_remote_apic(apicid);
|
|
#endif
|
|
}
|
|
}
|
|
if (boot_error) {
|
|
cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
|
|
clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
|
|
cpucount--;
|
|
x86_cpu_to_apicid[cpu] = BAD_APICID;
|
|
x86_cpu_to_log_apicid[cpu] = BAD_APICID;
|
|
}
|
|
}
|
|
|
|
static void smp_tune_scheduling (void)
|
|
{
|
|
int cachesize; /* kB */
|
|
unsigned long bandwidth = 1000; /* MB/s */
|
|
/*
|
|
* Rough estimation for SMP scheduling, this is the number of
|
|
* cycles it takes for a fully memory-limited process to flush
|
|
* the SMP-local cache.
|
|
*
|
|
* (For a P5 this pretty much means we will choose another idle
|
|
* CPU almost always at wakeup time (this is due to the small
|
|
* L1 cache), on PIIs it's around 50-100 usecs, depending on
|
|
* the cache size)
|
|
*/
|
|
|
|
if (!cpu_khz) {
|
|
return;
|
|
} else {
|
|
cachesize = boot_cpu_data.x86_cache_size;
|
|
if (cachesize == -1) {
|
|
cachesize = 16; /* Pentiums, 2x8kB cache */
|
|
bandwidth = 100;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Cycle through the processors sending APIC IPIs to boot each.
|
|
*/
|
|
|
|
static void __init smp_boot_cpus(unsigned int max_cpus)
|
|
{
|
|
unsigned apicid, cpu, bit, kicked;
|
|
|
|
nmi_watchdog_default();
|
|
|
|
/*
|
|
* Setup boot CPU information
|
|
*/
|
|
smp_store_cpu_info(0); /* Final full version of the data */
|
|
printk(KERN_INFO "CPU%d: ", 0);
|
|
print_cpu_info(&cpu_data[0]);
|
|
|
|
current_thread_info()->cpu = 0;
|
|
smp_tune_scheduling();
|
|
|
|
if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
|
|
printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
hard_smp_processor_id());
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* If we couldn't find an SMP configuration at boot time,
|
|
* get out of here now!
|
|
*/
|
|
if (!smp_found_config) {
|
|
printk(KERN_NOTICE "SMP motherboard not detected.\n");
|
|
io_apic_irqs = 0;
|
|
cpu_online_map = cpumask_of_cpu(0);
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
if (APIC_init_uniprocessor())
|
|
printk(KERN_NOTICE "Local APIC not detected."
|
|
" Using dummy APIC emulation.\n");
|
|
goto smp_done;
|
|
}
|
|
|
|
/*
|
|
* Should not be necessary because the MP table should list the boot
|
|
* CPU too, but we do it for the sake of robustness anyway.
|
|
*/
|
|
if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
|
|
printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
boot_cpu_id);
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* If we couldn't find a local APIC, then get out of here now!
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
|
|
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
|
boot_cpu_id);
|
|
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
|
|
io_apic_irqs = 0;
|
|
cpu_online_map = cpumask_of_cpu(0);
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
disable_apic = 1;
|
|
goto smp_done;
|
|
}
|
|
|
|
verify_local_APIC();
|
|
|
|
/*
|
|
* If SMP should be disabled, then really disable it!
|
|
*/
|
|
if (!max_cpus) {
|
|
smp_found_config = 0;
|
|
printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
|
|
io_apic_irqs = 0;
|
|
cpu_online_map = cpumask_of_cpu(0);
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
disable_apic = 1;
|
|
goto smp_done;
|
|
}
|
|
|
|
connect_bsp_APIC();
|
|
setup_local_APIC();
|
|
|
|
if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
|
|
BUG();
|
|
|
|
x86_cpu_to_apicid[0] = boot_cpu_id;
|
|
|
|
/*
|
|
* Now scan the CPU present map and fire up the other CPUs.
|
|
*/
|
|
Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
|
|
|
|
kicked = 1;
|
|
for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
|
|
apicid = cpu_present_to_apicid(bit);
|
|
/*
|
|
* Don't even attempt to start the boot CPU!
|
|
*/
|
|
if (apicid == boot_cpu_id || (apicid == BAD_APICID))
|
|
continue;
|
|
|
|
if (!physid_isset(apicid, phys_cpu_present_map))
|
|
continue;
|
|
if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
|
|
continue;
|
|
|
|
do_boot_cpu(apicid);
|
|
++kicked;
|
|
}
|
|
|
|
/*
|
|
* Cleanup possible dangling ends...
|
|
*/
|
|
{
|
|
/*
|
|
* Install writable page 0 entry to set BIOS data area.
|
|
*/
|
|
local_flush_tlb();
|
|
|
|
/*
|
|
* Paranoid: Set warm reset code and vector here back
|
|
* to default values.
|
|
*/
|
|
CMOS_WRITE(0, 0xf);
|
|
|
|
*((volatile int *) phys_to_virt(0x467)) = 0;
|
|
}
|
|
|
|
/*
|
|
* Allow the user to impress friends.
|
|
*/
|
|
|
|
Dprintk("Before bogomips.\n");
|
|
if (!cpucount) {
|
|
printk(KERN_INFO "Only one processor found.\n");
|
|
} else {
|
|
unsigned long bogosum = 0;
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++)
|
|
if (cpu_isset(cpu, cpu_callout_map))
|
|
bogosum += cpu_data[cpu].loops_per_jiffy;
|
|
printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
|
|
cpucount+1,
|
|
bogosum/(500000/HZ),
|
|
(bogosum/(5000/HZ))%100);
|
|
Dprintk("Before bogocount - setting activated=1.\n");
|
|
}
|
|
|
|
/*
|
|
* Construct cpu_sibling_map[], so that we can tell the
|
|
* sibling CPU efficiently.
|
|
*/
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++)
|
|
cpus_clear(cpu_sibling_map[cpu]);
|
|
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++) {
|
|
int siblings = 0;
|
|
int i;
|
|
if (!cpu_isset(cpu, cpu_callout_map))
|
|
continue;
|
|
|
|
if (smp_num_siblings > 1) {
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
if (!cpu_isset(i, cpu_callout_map))
|
|
continue;
|
|
if (phys_proc_id[cpu] == phys_proc_id[i]) {
|
|
siblings++;
|
|
cpu_set(i, cpu_sibling_map[cpu]);
|
|
}
|
|
}
|
|
} else {
|
|
siblings++;
|
|
cpu_set(cpu, cpu_sibling_map[cpu]);
|
|
}
|
|
|
|
if (siblings != smp_num_siblings) {
|
|
printk(KERN_WARNING
|
|
"WARNING: %d siblings found for CPU%d, should be %d\n",
|
|
siblings, cpu, smp_num_siblings);
|
|
smp_num_siblings = siblings;
|
|
}
|
|
}
|
|
|
|
Dprintk("Boot done.\n");
|
|
|
|
/*
|
|
* Here we can be sure that there is an IO-APIC in the system. Let's
|
|
* go and set it up:
|
|
*/
|
|
if (!skip_ioapic_setup && nr_ioapics)
|
|
setup_IO_APIC();
|
|
else
|
|
nr_ioapics = 0;
|
|
|
|
setup_boot_APIC_clock();
|
|
|
|
/*
|
|
* Synchronize the TSC with the AP
|
|
*/
|
|
if (cpu_has_tsc && cpucount)
|
|
synchronize_tsc_bp();
|
|
|
|
smp_done:
|
|
time_init_smp();
|
|
}
|
|
|
|
/* These are wrappers to interface to the new boot process. Someone
|
|
who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
smp_boot_cpus(max_cpus);
|
|
}
|
|
|
|
void __devinit smp_prepare_boot_cpu(void)
|
|
{
|
|
cpu_set(smp_processor_id(), cpu_online_map);
|
|
cpu_set(smp_processor_id(), cpu_callout_map);
|
|
}
|
|
|
|
int __devinit __cpu_up(unsigned int cpu)
|
|
{
|
|
/* This only works at boot for x86. See "rewrite" above. */
|
|
if (cpu_isset(cpu, smp_commenced_mask)) {
|
|
local_irq_enable();
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/* In case one didn't come up */
|
|
if (!cpu_isset(cpu, cpu_callin_map)) {
|
|
local_irq_enable();
|
|
return -EIO;
|
|
}
|
|
local_irq_enable();
|
|
|
|
/* Unleash the CPU! */
|
|
Dprintk("waiting for cpu %d\n", cpu);
|
|
|
|
cpu_set(cpu, smp_commenced_mask);
|
|
while (!cpu_isset(cpu, cpu_online_map))
|
|
mb();
|
|
return 0;
|
|
}
|
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
setup_ioapic_dest();
|
|
#endif
|
|
zap_low_mappings();
|
|
}
|
|
|