forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
711 lines
16 KiB
C
711 lines
16 KiB
C
/*
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* Driver for the Macintosh 68K onboard MACE controller with PSC
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* driven DMA. The MACE driver code is derived from mace.c. The
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* Mac68k theory of operation is courtesy of the MacBSD wizards.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1998 Alan Cox <alan@redhat.com>
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*
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* Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/crc32.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/macintosh.h>
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#include <asm/macints.h>
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#include <asm/mac_psc.h>
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#include <asm/page.h>
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#include "mace.h"
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#define N_TX_RING 1
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#define N_RX_RING 8
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#define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE)
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#define TX_TIMEOUT HZ
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/* Bits in transmit DMA status */
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#define TX_DMA_ERR 0x80
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/* The MACE is simply wired down on a Mac68K box */
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#define MACE_BASE (void *)(0x50F1C000)
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#define MACE_PROM (void *)(0x50F08001)
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struct mace_data {
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volatile struct mace *mace;
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volatile unsigned char *tx_ring;
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volatile unsigned char *tx_ring_phys;
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volatile unsigned char *rx_ring;
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volatile unsigned char *rx_ring_phys;
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int dma_intr;
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struct net_device_stats stats;
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int rx_slot, rx_tail;
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int tx_slot, tx_sloti, tx_count;
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};
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struct mace_frame {
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u16 len;
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u16 status;
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u16 rntpc;
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u16 rcvcc;
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u32 pad1;
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u32 pad2;
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u8 data[1];
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/* And frame continues.. */
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};
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#define PRIV_BYTES sizeof(struct mace_data)
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extern void psc_debug_dump(void);
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static int mace_open(struct net_device *dev);
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static int mace_close(struct net_device *dev);
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static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
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static struct net_device_stats *mace_stats(struct net_device *dev);
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static void mace_set_multicast(struct net_device *dev);
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static int mace_set_address(struct net_device *dev, void *addr);
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static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
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static irqreturn_t mace_dma_intr(int irq, void *dev_id, struct pt_regs *regs);
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static void mace_tx_timeout(struct net_device *dev);
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/* Bit-reverse one byte of an ethernet hardware address. */
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static int bitrev(int b)
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{
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int d = 0, i;
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for (i = 0; i < 8; ++i, b >>= 1) {
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d = (d << 1) | (b & 1);
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}
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return d;
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}
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/*
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* Load a receive DMA channel with a base address and ring length
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*/
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static void mace_load_rxdma_base(struct net_device *dev, int set)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
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psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
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psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
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psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
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mp->rx_tail = 0;
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}
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/*
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* Reset the receive DMA subsystem
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*/
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static void mace_rxdma_reset(struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mace = mp->mace;
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u8 maccc = mace->maccc;
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mace->maccc = maccc & ~ENRCV;
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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mace_load_rxdma_base(dev, 0x00);
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psc_write_word(PSC_ENETRD_CTL, 0x0400);
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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mace_load_rxdma_base(dev, 0x10);
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psc_write_word(PSC_ENETRD_CTL, 0x0400);
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mace->maccc = maccc;
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mp->rx_slot = 0;
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psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
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}
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/*
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* Reset the transmit DMA subsystem
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*/
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static void mace_txdma_reset(struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mace = mp->mace;
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u8 maccc;
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psc_write_word(PSC_ENETWR_CTL, 0x8800);
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maccc = mace->maccc;
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mace->maccc = maccc & ~ENXMT;
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mp->tx_slot = mp->tx_sloti = 0;
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mp->tx_count = N_TX_RING;
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psc_write_word(PSC_ENETWR_CTL, 0x0400);
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mace->maccc = maccc;
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}
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/*
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* Disable DMA
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*/
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static void mace_dma_off(struct net_device *dev)
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{
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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psc_write_word(PSC_ENETRD_CTL, 0x1000);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
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psc_write_word(PSC_ENETWR_CTL, 0x8800);
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psc_write_word(PSC_ENETWR_CTL, 0x1000);
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psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
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psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
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}
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/*
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* Not really much of a probe. The hardware table tells us if this
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* model of Macintrash has a MACE (AV macintoshes)
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*/
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struct net_device *mace_probe(int unit)
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{
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int j;
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struct mace_data *mp;
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unsigned char *addr;
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struct net_device *dev;
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unsigned char checksum = 0;
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static int found = 0;
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int err;
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if (found || macintosh_config->ether_type != MAC_ETHER_MACE)
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return ERR_PTR(-ENODEV);
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found = 1; /* prevent 'finding' one on every device probe */
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dev = alloc_etherdev(PRIV_BYTES);
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if (!dev)
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return ERR_PTR(-ENOMEM);
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if (unit >= 0)
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sprintf(dev->name, "eth%d", unit);
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mp = (struct mace_data *) dev->priv;
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dev->base_addr = (u32)MACE_BASE;
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mp->mace = (volatile struct mace *) MACE_BASE;
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dev->irq = IRQ_MAC_MACE;
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mp->dma_intr = IRQ_MAC_MACE_DMA;
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/*
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* The PROM contains 8 bytes which total 0xFF when XOR'd
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* together. Due to the usual peculiar apple brain damage
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* the bytes are spaced out in a strange boundary and the
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* bits are reversed.
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*/
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addr = (void *)MACE_PROM;
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for (j = 0; j < 6; ++j) {
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u8 v=bitrev(addr[j<<4]);
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checksum ^= v;
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dev->dev_addr[j] = v;
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}
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for (; j < 8; ++j) {
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checksum ^= bitrev(addr[j<<4]);
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}
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if (checksum != 0xFF) {
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free_netdev(dev);
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return ERR_PTR(-ENODEV);
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}
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memset(&mp->stats, 0, sizeof(mp->stats));
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dev->open = mace_open;
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dev->stop = mace_close;
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dev->hard_start_xmit = mace_xmit_start;
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dev->tx_timeout = mace_tx_timeout;
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dev->watchdog_timeo = TX_TIMEOUT;
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dev->get_stats = mace_stats;
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dev->set_multicast_list = mace_set_multicast;
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dev->set_mac_address = mace_set_address;
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printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]);
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for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]);
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printk("\n");
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err = register_netdev(dev);
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if (!err)
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return dev;
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free_netdev(dev);
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return ERR_PTR(err);
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}
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/*
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* Load the address on a mace controller.
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*/
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static int mace_set_address(struct net_device *dev, void *addr)
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{
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unsigned char *p = addr;
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mb = mp->mace;
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int i;
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unsigned long flags;
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u8 maccc;
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local_irq_save(flags);
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maccc = mb->maccc;
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/* load up the hardware address */
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mb->iac = ADDRCHG | PHYADDR;
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while ((mb->iac & ADDRCHG) != 0);
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for (i = 0; i < 6; ++i) {
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mb->padr = dev->dev_addr[i] = p[i];
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}
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mb->maccc = maccc;
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local_irq_restore(flags);
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return 0;
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}
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/*
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* Open the Macintosh MACE. Most of this is playing with the DMA
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* engine. The ethernet chip is quite friendly.
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*/
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static int mace_open(struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mb = mp->mace;
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#if 0
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int i;
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i = 200;
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while (--i) {
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mb->biucc = SWRST;
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if (mb->biucc & SWRST) {
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udelay(10);
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continue;
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}
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break;
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}
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if (!i) {
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printk(KERN_ERR "%s: software reset failed!!\n", dev->name);
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return -EAGAIN;
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}
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#endif
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mb->biucc = XMTSP_64;
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mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST;
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mb->xmtfc = AUTO_PAD_XMIT;
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mb->plscc = PORTSEL_AUI;
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/* mb->utr = RTRD; */
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if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
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printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
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return -EAGAIN;
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}
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if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
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printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
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free_irq(dev->irq, dev);
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return -EAGAIN;
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}
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/* Allocate the DMA ring buffers */
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mp->rx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, N_RX_PAGES);
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mp->tx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
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if (mp->tx_ring==NULL || mp->rx_ring==NULL) {
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if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES);
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if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0);
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free_irq(dev->irq, dev);
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free_irq(mp->dma_intr, dev);
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printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name);
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return -ENOMEM;
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}
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mp->rx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->rx_ring);
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mp->tx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->tx_ring);
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/* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */
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kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER);
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kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH);
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mace_dma_off(dev);
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/* Not sure what these do */
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psc_write_word(PSC_ENETWR_CTL, 0x9000);
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psc_write_word(PSC_ENETRD_CTL, 0x9000);
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psc_write_word(PSC_ENETWR_CTL, 0x0400);
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psc_write_word(PSC_ENETRD_CTL, 0x0400);
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#if 0
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/* load up the hardware address */
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mb->iac = ADDRCHG | PHYADDR;
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while ((mb->iac & ADDRCHG) != 0);
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for (i = 0; i < 6; ++i)
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mb->padr = dev->dev_addr[i];
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/* clear the multicast filter */
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mb->iac = ADDRCHG | LOGADDR;
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while ((mb->iac & ADDRCHG) != 0);
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for (i = 0; i < 8; ++i)
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mb->ladrf = 0;
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mb->plscc = PORTSEL_GPSI + ENPLSIO;
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mb->maccc = ENXMT | ENRCV;
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mb->imr = RCVINT;
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#endif
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mace_rxdma_reset(dev);
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mace_txdma_reset(dev);
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return 0;
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}
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/*
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* Shut down the mace and its interrupt channel
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*/
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static int mace_close(struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mb = mp->mace;
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mb->maccc = 0; /* disable rx and tx */
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mb->imr = 0xFF; /* disable all irqs */
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mace_dma_off(dev); /* disable rx and tx dma */
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free_irq(dev->irq, dev);
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free_irq(IRQ_MAC_MACE_DMA, dev);
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free_pages((u32) mp->rx_ring, N_RX_PAGES);
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free_pages((u32) mp->tx_ring, 0);
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return 0;
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}
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/*
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* Transmit a frame
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*/
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static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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/* Stop the queue if the buffer is full */
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if (!mp->tx_count) {
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netif_stop_queue(dev);
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return 1;
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}
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mp->tx_count--;
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mp->stats.tx_packets++;
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mp->stats.tx_bytes += skb->len;
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/* We need to copy into our xmit buffer to take care of alignment and caching issues */
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memcpy((void *) mp->tx_ring, skb->data, skb->len);
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/* load the Tx DMA and fire it off */
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psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
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psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
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psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
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mp->tx_slot ^= 0x10;
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dev_kfree_skb(skb);
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return 0;
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}
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static struct net_device_stats *mace_stats(struct net_device *dev)
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{
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struct mace_data *p = (struct mace_data *) dev->priv;
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return &p->stats;
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}
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static void mace_set_multicast(struct net_device *dev)
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{
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struct mace_data *mp = (struct mace_data *) dev->priv;
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volatile struct mace *mb = mp->mace;
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int i, j;
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u32 crc;
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u8 maccc;
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maccc = mb->maccc;
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mb->maccc &= ~PROM;
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if (dev->flags & IFF_PROMISC) {
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mb->maccc |= PROM;
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} else {
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unsigned char multicast_filter[8];
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struct dev_mc_list *dmi = dev->mc_list;
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if (dev->flags & IFF_ALLMULTI) {
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for (i = 0; i < 8; i++) {
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multicast_filter[i] = 0xFF;
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}
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} else {
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for (i = 0; i < 8; i++)
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multicast_filter[i] = 0;
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for (i = 0; i < dev->mc_count; i++) {
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crc = ether_crc_le(6, dmi->dmi_addr);
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j = crc >> 26; /* bit number in multicast_filter */
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multicast_filter[j >> 3] |= 1 << (j & 7);
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dmi = dmi->next;
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}
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}
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mb->iac = ADDRCHG | LOGADDR;
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while (mb->iac & ADDRCHG);
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for (i = 0; i < 8; ++i) {
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mb->ladrf = multicast_filter[i];
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}
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}
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mb->maccc = maccc;
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}
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/*
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* Miscellaneous interrupts are handled here. We may end up
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* having to bash the chip on the head for bad errors
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*/
|
|
|
|
static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
|
|
{
|
|
volatile struct mace *mb = mp->mace;
|
|
static int mace_babbles, mace_jabbers;
|
|
|
|
if (intr & MPCO) {
|
|
mp->stats.rx_missed_errors += 256;
|
|
}
|
|
mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */
|
|
|
|
if (intr & RNTPCO) {
|
|
mp->stats.rx_length_errors += 256;
|
|
}
|
|
mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */
|
|
|
|
if (intr & CERR) {
|
|
++mp->stats.tx_heartbeat_errors;
|
|
}
|
|
if (intr & BABBLE) {
|
|
if (mace_babbles++ < 4) {
|
|
printk(KERN_DEBUG "mace: babbling transmitter\n");
|
|
}
|
|
}
|
|
if (intr & JABBER) {
|
|
if (mace_jabbers++ < 4) {
|
|
printk(KERN_DEBUG "mace: jabbering transceiver\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* A transmit error has occurred. (We kick the transmit side from
|
|
* the DMA completion)
|
|
*/
|
|
|
|
static void mace_xmit_error(struct net_device *dev)
|
|
{
|
|
struct mace_data *mp = (struct mace_data *) dev->priv;
|
|
volatile struct mace *mb = mp->mace;
|
|
u8 xmtfs, xmtrc;
|
|
|
|
xmtfs = mb->xmtfs;
|
|
xmtrc = mb->xmtrc;
|
|
|
|
if (xmtfs & XMTSV) {
|
|
if (xmtfs & UFLO) {
|
|
printk("%s: DMA underrun.\n", dev->name);
|
|
mp->stats.tx_errors++;
|
|
mp->stats.tx_fifo_errors++;
|
|
mace_txdma_reset(dev);
|
|
}
|
|
if (xmtfs & RTRY) {
|
|
mp->stats.collisions++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* A receive interrupt occurred.
|
|
*/
|
|
|
|
static void mace_recv_interrupt(struct net_device *dev)
|
|
{
|
|
/* struct mace_data *mp = (struct mace_data *) dev->priv; */
|
|
// volatile struct mace *mb = mp->mace;
|
|
}
|
|
|
|
/*
|
|
* Process the chip interrupt
|
|
*/
|
|
|
|
static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct net_device *dev = (struct net_device *) dev_id;
|
|
struct mace_data *mp = (struct mace_data *) dev->priv;
|
|
volatile struct mace *mb = mp->mace;
|
|
u8 ir;
|
|
|
|
ir = mb->ir;
|
|
mace_handle_misc_intrs(mp, ir);
|
|
|
|
if (ir & XMTINT) {
|
|
mace_xmit_error(dev);
|
|
}
|
|
if (ir & RCVINT) {
|
|
mace_recv_interrupt(dev);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void mace_tx_timeout(struct net_device *dev)
|
|
{
|
|
/* struct mace_data *mp = (struct mace_data *) dev->priv; */
|
|
// volatile struct mace *mb = mp->mace;
|
|
}
|
|
|
|
/*
|
|
* Handle a newly arrived frame
|
|
*/
|
|
|
|
static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
|
|
{
|
|
struct mace_data *mp = (struct mace_data *) dev->priv;
|
|
struct sk_buff *skb;
|
|
|
|
if (mf->status & RS_OFLO) {
|
|
printk("%s: fifo overflow.\n", dev->name);
|
|
mp->stats.rx_errors++;
|
|
mp->stats.rx_fifo_errors++;
|
|
}
|
|
if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
|
|
mp->stats.rx_errors++;
|
|
|
|
if (mf->status&RS_CLSN) {
|
|
mp->stats.collisions++;
|
|
}
|
|
if (mf->status&RS_FRAMERR) {
|
|
mp->stats.rx_frame_errors++;
|
|
}
|
|
if (mf->status&RS_FCSERR) {
|
|
mp->stats.rx_crc_errors++;
|
|
}
|
|
|
|
skb = dev_alloc_skb(mf->len+2);
|
|
if (!skb) {
|
|
mp->stats.rx_dropped++;
|
|
return;
|
|
}
|
|
skb_reserve(skb,2);
|
|
memcpy(skb_put(skb, mf->len), mf->data, mf->len);
|
|
|
|
skb->dev = dev;
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
netif_rx(skb);
|
|
dev->last_rx = jiffies;
|
|
mp->stats.rx_packets++;
|
|
mp->stats.rx_bytes += mf->len;
|
|
}
|
|
|
|
/*
|
|
* The PSC has passed us a DMA interrupt event.
|
|
*/
|
|
|
|
static irqreturn_t mace_dma_intr(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct net_device *dev = (struct net_device *) dev_id;
|
|
struct mace_data *mp = (struct mace_data *) dev->priv;
|
|
int left, head;
|
|
u16 status;
|
|
u32 baka;
|
|
|
|
/* Not sure what this does */
|
|
|
|
while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
|
|
if (!(baka & 0x60000000)) return IRQ_NONE;
|
|
|
|
/*
|
|
* Process the read queue
|
|
*/
|
|
|
|
status = psc_read_word(PSC_ENETRD_CTL);
|
|
|
|
if (status & 0x2000) {
|
|
mace_rxdma_reset(dev);
|
|
} else if (status & 0x0100) {
|
|
psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
|
|
|
|
left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
|
|
head = N_RX_RING - left;
|
|
|
|
/* Loop through the ring buffer and process new packages */
|
|
|
|
while (mp->rx_tail < head) {
|
|
mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800)));
|
|
mp->rx_tail++;
|
|
}
|
|
|
|
/* If we're out of buffers in this ring then switch to */
|
|
/* the other set, otherwise just reactivate this one. */
|
|
|
|
if (!left) {
|
|
mace_load_rxdma_base(dev, mp->rx_slot);
|
|
mp->rx_slot ^= 0x10;
|
|
} else {
|
|
psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Process the write queue
|
|
*/
|
|
|
|
status = psc_read_word(PSC_ENETWR_CTL);
|
|
|
|
if (status & 0x2000) {
|
|
mace_txdma_reset(dev);
|
|
} else if (status & 0x0100) {
|
|
psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
|
|
mp->tx_sloti ^= 0x10;
|
|
mp->tx_count++;
|
|
netif_wake_queue(dev);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|