forked from luck/tmp_suning_uos_patched
6eac402783
The current CONFIG_M532x support definitions are actually common to a larger set of version 3 ColdFire CPU types. In the future we want to add support for the 537x family. It is very similar to the 532x internally, and will be able to use most of the same definitions. Create a CONFIG_M53xx option that is enabled to support any of the common 532x and 537x CPU types. Convert the current users of CONFIG_M532x to use CONFIG_M53xx instead. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/****************************************************************************/
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/*
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* mcftimer.h -- ColdFire internal TIMER support defines.
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*
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* (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef mcftimer_h
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#define mcftimer_h
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/****************************************************************************/
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/*
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* Define the TIMER register set addresses.
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*/
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#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
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#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
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#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
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#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
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#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
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#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
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#else
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#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
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#endif
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/*
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* Bit definitions for the Timer Mode Register (TMR).
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* Register bit flags are common across ColdFires.
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*/
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#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
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#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
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#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
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#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
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#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
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#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
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#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
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#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
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#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
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#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
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#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
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#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
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#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
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#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
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#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
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#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
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#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
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/*
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* Bit definitions for the Timer Event Registers (TER).
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*/
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#define MCFTIMER_TER_CAP 0x01 /* Capture event */
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#define MCFTIMER_TER_REF 0x02 /* Refernece event */
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/****************************************************************************/
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#endif /* mcftimer_h */
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