forked from luck/tmp_suning_uos_patched
6d5db46687
Minor formatting fixup since the information which core was associated with the MCE is not always valid. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
921 lines
18 KiB
C
921 lines
18 KiB
C
#include <linux/module.h>
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#include <linux/slab.h>
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#include "mce_amd.h"
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static struct amd_decoder_ops *fam_ops;
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static u8 xec_mask = 0xf;
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static u8 nb_err_cpumask = 0xf;
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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nb_bus_decoder = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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/* transaction type */
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const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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EXPORT_SYMBOL_GPL(tt_msgs);
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/* cache level */
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const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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EXPORT_SYMBOL_GPL(ll_msgs);
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/* memory transaction type */
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const char *rrrr_msgs[] = {
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"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
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};
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EXPORT_SYMBOL_GPL(rrrr_msgs);
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/* participating processor */
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const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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EXPORT_SYMBOL_GPL(pp_msgs);
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/* request timeout */
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const char *to_msgs[] = { "no timeout", "timed out" };
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EXPORT_SYMBOL_GPL(to_msgs);
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/* memory or i/o */
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const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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EXPORT_SYMBOL_GPL(ii_msgs);
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static const char *f10h_nb_mce_desc[] = {
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"HT link data error",
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"Protocol error (link, L3, probe filter, etc.)",
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"Parity error in NB-internal arrays",
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"Link Retry due to IO link transmission error",
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"L3 ECC data cache error",
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"ECC error in L3 cache tag",
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"L3 LRU parity bits error",
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"ECC Error in the Probe Filter directory"
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};
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static const char * const f15h_ic_mce_desc[] = {
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"UC during a demand linefill from L2",
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"Parity error during data load from IC",
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"Parity error for IC valid bit",
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"Main tag parity error",
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"Parity error in prediction queue",
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"PFB data/address parity error",
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"Parity error in the branch status reg",
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"PFB promotion address error",
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"Tag error during probe/victimization",
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"Parity error for IC probe tag valid bit",
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"PFB non-cacheable bit parity error",
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"PFB valid bit parity error", /* xec = 0xd */
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"patch RAM", /* xec = 010 */
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"uop queue",
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"insn buffer",
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"predecode buffer",
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"fetch address FIFO"
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};
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static const char * const f15h_cu_mce_desc[] = {
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"Fill ECC error on data fills", /* xec = 0x4 */
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"Fill parity error on insn fills",
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"Prefetcher request FIFO parity error",
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"PRQ address parity error",
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"PRQ data parity error",
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"WCC Tag ECC error",
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"WCC Data ECC error",
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"WCB Data parity error",
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"VB Data/ECC error",
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"L2 Tag ECC error", /* xec = 0x10 */
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"Hard L2 Tag ECC error",
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"Multiple hits on L2 tag",
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"XAB parity error",
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"PRB address parity error"
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};
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static const char * const fr_ex_mce_desc[] = {
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"CPU Watchdog timer expire",
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"Wakeup array dest tag",
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"AG payload array",
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"EX payload array",
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"IDRF array",
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"Retire dispatch queue",
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"Mapper checkpoint array",
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"Physical register file EX0 port",
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"Physical register file EX1 port",
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"Physical register file AG0 port",
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"Physical register file AG1 port",
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"Flag register file",
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"DE correctable error could not be corrected"
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};
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static bool f12h_dc_mce(u16 ec, u8 xec)
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{
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bool ret = false;
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if (MEM_ERROR(ec)) {
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u8 ll = LL(ec);
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ret = true;
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if (ll == LL_L2)
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pr_cont("during L1 linefill from L2.\n");
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else if (ll == LL_L1)
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pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
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else
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ret = false;
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}
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return ret;
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}
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static bool f10h_dc_mce(u16 ec, u8 xec)
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{
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if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
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pr_cont("during data scrub.\n");
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return true;
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}
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return f12h_dc_mce(ec, xec);
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}
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static bool k8_dc_mce(u16 ec, u8 xec)
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{
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if (BUS_ERROR(ec)) {
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pr_cont("during system linefill.\n");
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return true;
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}
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return f10h_dc_mce(ec, xec);
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}
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static bool f14h_dc_mce(u16 ec, u8 xec)
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{
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u8 r4 = R4(ec);
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bool ret = true;
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if (MEM_ERROR(ec)) {
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if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
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return false;
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switch (r4) {
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case R4_DRD:
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case R4_DWR:
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pr_cont("Data/Tag parity error due to %s.\n",
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(r4 == R4_DRD ? "load/hw prf" : "store"));
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break;
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case R4_EVICT:
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pr_cont("Copyback parity error on a tag miss.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag parity error during snoop.\n");
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break;
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default:
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ret = false;
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}
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} else if (BUS_ERROR(ec)) {
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if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
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return false;
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pr_cont("System read data error on a ");
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switch (r4) {
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case R4_RD:
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pr_cont("TLB reload.\n");
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break;
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case R4_DWR:
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pr_cont("store.\n");
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break;
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case R4_DRD:
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pr_cont("load.\n");
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break;
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default:
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ret = false;
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}
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} else {
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ret = false;
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}
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return ret;
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}
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static bool f15h_dc_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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if (MEM_ERROR(ec)) {
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switch (xec) {
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case 0x0:
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pr_cont("Data Array access error.\n");
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break;
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case 0x1:
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pr_cont("UC error during a linefill from L2/NB.\n");
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break;
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case 0x2:
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case 0x11:
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pr_cont("STQ access error.\n");
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break;
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case 0x3:
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pr_cont("SCB access error.\n");
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break;
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case 0x10:
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pr_cont("Tag error.\n");
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break;
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case 0x12:
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pr_cont("LDQ access error.\n");
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break;
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default:
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ret = false;
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}
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} else if (BUS_ERROR(ec)) {
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if (!xec)
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pr_cont("during system linefill.\n");
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else
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pr_cont(" Internal %s condition.\n",
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((xec == 1) ? "livelock" : "deadlock"));
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} else
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ret = false;
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return ret;
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}
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static void amd_decode_dc_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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pr_emerg(HW_ERR "Data Cache Error: ");
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/* TLB error signatures are the same across families */
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if (TLB_ERROR(ec)) {
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if (TT(ec) == TT_DATA) {
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pr_cont("%s TLB %s.\n", LL_MSG(ec),
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((xec == 2) ? "locked miss"
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: (xec ? "multimatch" : "parity")));
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return;
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}
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} else if (fam_ops->dc_mce(ec, xec))
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;
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else
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pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
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}
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static bool k8_ic_mce(u16 ec, u8 xec)
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{
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u8 ll = LL(ec);
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bool ret = true;
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if (!MEM_ERROR(ec))
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return false;
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if (ll == 0x2)
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pr_cont("during a linefill from L2.\n");
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else if (ll == 0x1) {
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switch (R4(ec)) {
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case R4_IRD:
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pr_cont("Parity error during data load.\n");
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break;
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case R4_EVICT:
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pr_cont("Copyback Parity/Victim error.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag Snoop error.\n");
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break;
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default:
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ret = false;
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break;
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}
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} else
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ret = false;
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return ret;
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}
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static bool f14h_ic_mce(u16 ec, u8 xec)
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{
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u8 r4 = R4(ec);
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bool ret = true;
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if (MEM_ERROR(ec)) {
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if (TT(ec) != 0 || LL(ec) != 1)
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ret = false;
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if (r4 == R4_IRD)
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pr_cont("Data/tag array parity error for a tag hit.\n");
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else if (r4 == R4_SNOOP)
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pr_cont("Tag error during snoop/victimization.\n");
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else
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ret = false;
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}
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return ret;
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}
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static bool f15h_ic_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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if (!MEM_ERROR(ec))
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return false;
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switch (xec) {
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case 0x0 ... 0xa:
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pr_cont("%s.\n", f15h_ic_mce_desc[xec]);
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break;
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case 0xd:
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pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
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break;
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case 0x10 ... 0x14:
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pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
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break;
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default:
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ret = false;
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}
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return ret;
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}
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static void amd_decode_ic_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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pr_emerg(HW_ERR "Instruction Cache Error: ");
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if (TLB_ERROR(ec))
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pr_cont("%s TLB %s.\n", LL_MSG(ec),
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(xec ? "multimatch" : "parity error"));
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else if (BUS_ERROR(ec)) {
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bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
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pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
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} else if (fam_ops->ic_mce(ec, xec))
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;
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else
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pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
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}
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static void amd_decode_bu_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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pr_emerg(HW_ERR "Bus Unit Error");
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if (xec == 0x1)
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pr_cont(" in the write data buffers.\n");
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else if (xec == 0x3)
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pr_cont(" in the victim data buffers.\n");
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else if (xec == 0x2 && MEM_ERROR(ec))
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pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
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else if (xec == 0x0) {
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if (TLB_ERROR(ec))
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pr_cont(": %s error in a Page Descriptor Cache or "
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"Guest TLB.\n", TT_MSG(ec));
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else if (BUS_ERROR(ec))
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pr_cont(": %s/ECC error in data read from NB: %s.\n",
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R4_MSG(ec), PP_MSG(ec));
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else if (MEM_ERROR(ec)) {
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u8 r4 = R4(ec);
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if (r4 >= 0x7)
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pr_cont(": %s error during data copyback.\n",
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R4_MSG(ec));
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else if (r4 <= 0x1)
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pr_cont(": %s parity/ECC error during data "
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"access from L2.\n", R4_MSG(ec));
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else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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return;
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wrong_bu_mce:
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pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
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}
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static void amd_decode_cu_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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pr_emerg(HW_ERR "Combined Unit Error: ");
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if (TLB_ERROR(ec)) {
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if (xec == 0x0)
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pr_cont("Data parity TLB read error.\n");
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else if (xec == 0x1)
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pr_cont("Poison data provided for TLB fill.\n");
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else
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goto wrong_cu_mce;
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} else if (BUS_ERROR(ec)) {
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if (xec > 2)
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goto wrong_cu_mce;
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pr_cont("Error during attempted NB data read.\n");
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} else if (MEM_ERROR(ec)) {
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switch (xec) {
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case 0x4 ... 0xc:
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pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x4]);
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break;
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case 0x10 ... 0x14:
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pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x7]);
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break;
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default:
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goto wrong_cu_mce;
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}
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}
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return;
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wrong_cu_mce:
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pr_emerg(HW_ERR "Corrupted CU MCE info?\n");
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}
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static void amd_decode_ls_mce(struct mce *m)
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{
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, xec_mask);
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if (boot_cpu_data.x86 >= 0x14) {
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pr_emerg("You shouldn't be seeing an LS MCE on this cpu family,"
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" please report on LKML.\n");
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return;
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}
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pr_emerg(HW_ERR "Load Store Error");
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if (xec == 0x0) {
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u8 r4 = R4(ec);
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if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
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goto wrong_ls_mce;
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pr_cont(" during %s.\n", R4_MSG(ec));
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} else
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goto wrong_ls_mce;
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return;
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wrong_ls_mce:
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pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
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}
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static bool k8_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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switch (xec) {
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case 0x1:
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pr_cont("CRC error detected on HT link.\n");
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break;
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case 0x5:
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pr_cont("Invalid GART PTE entry during GART table walk.\n");
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break;
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case 0x6:
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pr_cont("Unsupported atomic RMW received from an IO link.\n");
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break;
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case 0x0:
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case 0x8:
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if (boot_cpu_data.x86 == 0x11)
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return false;
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pr_cont("DRAM ECC error detected on the NB.\n");
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break;
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case 0xd:
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pr_cont("Parity error on the DRAM addr/ctl signals.\n");
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break;
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default:
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ret = false;
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break;
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}
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return ret;
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}
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static bool f10h_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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u8 offset = 0;
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if (k8_nb_mce(ec, xec))
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return true;
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switch(xec) {
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case 0xa ... 0xc:
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offset = 10;
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break;
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case 0xe:
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offset = 11;
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break;
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case 0xf:
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|
if (TLB_ERROR(ec))
|
|
pr_cont("GART Table Walk data error.\n");
|
|
else if (BUS_ERROR(ec))
|
|
pr_cont("DMA Exclusion Vector Table Walk error.\n");
|
|
else
|
|
ret = false;
|
|
|
|
goto out;
|
|
break;
|
|
|
|
case 0x19:
|
|
if (boot_cpu_data.x86 == 0x15)
|
|
pr_cont("Compute Unit Data Error.\n");
|
|
else
|
|
ret = false;
|
|
|
|
goto out;
|
|
break;
|
|
|
|
case 0x1c ... 0x1f:
|
|
offset = 24;
|
|
break;
|
|
|
|
default:
|
|
ret = false;
|
|
|
|
goto out;
|
|
break;
|
|
}
|
|
|
|
pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static bool nb_noop_mce(u16 ec, u8 xec)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
|
|
{
|
|
u16 ec = EC(m->status);
|
|
u8 xec = XEC(m->status, 0x1f);
|
|
u32 nbsh = (u32)(m->status >> 32);
|
|
int core = -1;
|
|
|
|
pr_emerg(HW_ERR "Northbridge Error (node %d", node_id);
|
|
|
|
/* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */
|
|
if ((boot_cpu_data.x86 == 0x10) &&
|
|
(boot_cpu_data.x86_model > 7)) {
|
|
if (nbsh & K8_NBSH_ERR_CPU_VAL)
|
|
core = nbsh & nb_err_cpumask;
|
|
} else {
|
|
u8 assoc_cpus = nbsh & nb_err_cpumask;
|
|
|
|
if (assoc_cpus > 0)
|
|
core = fls(assoc_cpus) - 1;
|
|
}
|
|
|
|
if (core >= 0)
|
|
pr_cont(", core %d): ", core);
|
|
else
|
|
pr_cont("): ");
|
|
|
|
switch (xec) {
|
|
case 0x2:
|
|
pr_cont("Sync error (sync packets on HT link detected).\n");
|
|
return;
|
|
|
|
case 0x3:
|
|
pr_cont("HT Master abort.\n");
|
|
return;
|
|
|
|
case 0x4:
|
|
pr_cont("HT Target abort.\n");
|
|
return;
|
|
|
|
case 0x7:
|
|
pr_cont("NB Watchdog timeout.\n");
|
|
return;
|
|
|
|
case 0x9:
|
|
pr_cont("SVM DMA Exclusion Vector error.\n");
|
|
return;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!fam_ops->nb_mce(ec, xec))
|
|
goto wrong_nb_mce;
|
|
|
|
if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
|
|
if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
|
|
nb_bus_decoder(node_id, m, nbcfg);
|
|
|
|
return;
|
|
|
|
wrong_nb_mce:
|
|
pr_emerg(HW_ERR "Corrupted NB MCE info?\n");
|
|
}
|
|
EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
|
|
|
|
static void amd_decode_fr_mce(struct mce *m)
|
|
{
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
if (c->x86 == 0xf || c->x86 == 0x11)
|
|
goto wrong_fr_mce;
|
|
|
|
if (c->x86 != 0x15 && xec != 0x0)
|
|
goto wrong_fr_mce;
|
|
|
|
pr_emerg(HW_ERR "%s Error: ",
|
|
(c->x86 == 0x15 ? "Execution Unit" : "FIROB"));
|
|
|
|
if (xec == 0x0 || xec == 0xc)
|
|
pr_cont("%s.\n", fr_ex_mce_desc[xec]);
|
|
else if (xec < 0xd)
|
|
pr_cont("%s parity error.\n", fr_ex_mce_desc[xec]);
|
|
else
|
|
goto wrong_fr_mce;
|
|
|
|
return;
|
|
|
|
wrong_fr_mce:
|
|
pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
|
|
}
|
|
|
|
static void amd_decode_fp_mce(struct mce *m)
|
|
{
|
|
u8 xec = XEC(m->status, xec_mask);
|
|
|
|
pr_emerg(HW_ERR "Floating Point Unit Error: ");
|
|
|
|
switch (xec) {
|
|
case 0x1:
|
|
pr_cont("Free List");
|
|
break;
|
|
|
|
case 0x2:
|
|
pr_cont("Physical Register File");
|
|
break;
|
|
|
|
case 0x3:
|
|
pr_cont("Retire Queue");
|
|
break;
|
|
|
|
case 0x4:
|
|
pr_cont("Scheduler table");
|
|
break;
|
|
|
|
case 0x5:
|
|
pr_cont("Status Register File");
|
|
break;
|
|
|
|
default:
|
|
goto wrong_fp_mce;
|
|
break;
|
|
}
|
|
|
|
pr_cont(" parity error.\n");
|
|
|
|
return;
|
|
|
|
wrong_fp_mce:
|
|
pr_emerg(HW_ERR "Corrupted FP MCE info?\n");
|
|
}
|
|
|
|
static inline void amd_decode_err_code(u16 ec)
|
|
{
|
|
|
|
pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
|
|
|
|
if (BUS_ERROR(ec))
|
|
pr_cont(", mem/io: %s", II_MSG(ec));
|
|
else
|
|
pr_cont(", tx: %s", TT_MSG(ec));
|
|
|
|
if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
|
|
pr_cont(", mem-tx: %s", R4_MSG(ec));
|
|
|
|
if (BUS_ERROR(ec))
|
|
pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
|
|
}
|
|
|
|
pr_cont("\n");
|
|
}
|
|
|
|
/*
|
|
* Filter out unwanted MCE signatures here.
|
|
*/
|
|
static bool amd_filter_mce(struct mce *m)
|
|
{
|
|
u8 xec = (m->status >> 16) & 0x1f;
|
|
|
|
/*
|
|
* NB GART TLB error reporting is disabled by default.
|
|
*/
|
|
if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
|
|
{
|
|
struct mce *m = (struct mce *)data;
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
int node, ecc;
|
|
|
|
if (amd_filter_mce(m))
|
|
return NOTIFY_STOP;
|
|
|
|
pr_emerg(HW_ERR "MC%d_STATUS[%s|%s|%s|%s|%s",
|
|
m->bank,
|
|
((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
|
|
((m->status & MCI_STATUS_UC) ? "UE" : "CE"),
|
|
((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
|
|
((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
|
|
((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
|
|
|
|
if (c->x86 == 0x15)
|
|
pr_cont("|%s|%s",
|
|
((m->status & BIT_64(44)) ? "Deferred" : "-"),
|
|
((m->status & BIT_64(43)) ? "Poison" : "-"));
|
|
|
|
/* do the two bits[14:13] together */
|
|
ecc = (m->status >> 45) & 0x3;
|
|
if (ecc)
|
|
pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
|
|
|
|
pr_cont("]: 0x%016llx\n", m->status);
|
|
|
|
|
|
switch (m->bank) {
|
|
case 0:
|
|
amd_decode_dc_mce(m);
|
|
break;
|
|
|
|
case 1:
|
|
amd_decode_ic_mce(m);
|
|
break;
|
|
|
|
case 2:
|
|
if (c->x86 == 0x15)
|
|
amd_decode_cu_mce(m);
|
|
else
|
|
amd_decode_bu_mce(m);
|
|
break;
|
|
|
|
case 3:
|
|
amd_decode_ls_mce(m);
|
|
break;
|
|
|
|
case 4:
|
|
node = amd_get_nb_id(m->extcpu);
|
|
amd_decode_nb_mce(node, m, 0);
|
|
break;
|
|
|
|
case 5:
|
|
amd_decode_fr_mce(m);
|
|
break;
|
|
|
|
case 6:
|
|
amd_decode_fp_mce(m);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
amd_decode_err_code(m->status & 0xffff);
|
|
|
|
return NOTIFY_STOP;
|
|
}
|
|
EXPORT_SYMBOL_GPL(amd_decode_mce);
|
|
|
|
static struct notifier_block amd_mce_dec_nb = {
|
|
.notifier_call = amd_decode_mce,
|
|
};
|
|
|
|
static int __init mce_amd_init(void)
|
|
{
|
|
struct cpuinfo_x86 *c = &boot_cpu_data;
|
|
|
|
if (c->x86_vendor != X86_VENDOR_AMD)
|
|
return 0;
|
|
|
|
if ((c->x86 < 0xf || c->x86 > 0x12) &&
|
|
(c->x86 != 0x14 || c->x86_model > 0xf) &&
|
|
(c->x86 != 0x15 || c->x86_model > 0xf))
|
|
return 0;
|
|
|
|
fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
|
|
if (!fam_ops)
|
|
return -ENOMEM;
|
|
|
|
switch (c->x86) {
|
|
case 0xf:
|
|
fam_ops->dc_mce = k8_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = k8_nb_mce;
|
|
break;
|
|
|
|
case 0x10:
|
|
fam_ops->dc_mce = f10h_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = f10h_nb_mce;
|
|
break;
|
|
|
|
case 0x11:
|
|
fam_ops->dc_mce = k8_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = f10h_nb_mce;
|
|
break;
|
|
|
|
case 0x12:
|
|
fam_ops->dc_mce = f12h_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = nb_noop_mce;
|
|
break;
|
|
|
|
case 0x14:
|
|
nb_err_cpumask = 0x3;
|
|
fam_ops->dc_mce = f14h_dc_mce;
|
|
fam_ops->ic_mce = f14h_ic_mce;
|
|
fam_ops->nb_mce = nb_noop_mce;
|
|
break;
|
|
|
|
case 0x15:
|
|
xec_mask = 0x1f;
|
|
fam_ops->dc_mce = f15h_dc_mce;
|
|
fam_ops->ic_mce = f15h_ic_mce;
|
|
fam_ops->nb_mce = f10h_nb_mce;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_WARNING "Huh? What family is that: %d?!\n", c->x86);
|
|
kfree(fam_ops);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pr_info("MCE: In-kernel MCE decoding enabled.\n");
|
|
|
|
atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(mce_amd_init);
|
|
|
|
#ifdef MODULE
|
|
static void __exit mce_amd_exit(void)
|
|
{
|
|
atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
|
|
kfree(fam_ops);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("AMD MCE decoder");
|
|
MODULE_ALIAS("edac-mce-amd");
|
|
MODULE_LICENSE("GPL");
|
|
module_exit(mce_amd_exit);
|
|
#endif
|