AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity
248aa2645a
kernel_optimize_test/drivers/mtd/spi-nor
History
Miquel Raynal 8389a7b909 SPI NOR core changes: 
- introduce 'struct spi_nor_controller_ops',
 - clean the Register Operations methods,
 - use dev_dbg insted of dev_err for low level info,
 - fix retlen handling in sst_write(),
 - fix silent truncations in spi_nor_read and spi_nor_read_raw(),
 - fix the clearing of QE bit on lock()/unlock(),
 - rework the disabling of the block write protection,
 - rework the Quad Enable methods,
 - make sure nor->spimem and nor->controller_ops are mutually exclusive,
 - set default Quad Enable method for ISSI flashes,
 - add support for few flashes.
 
 SPI NOR controller drivers changes:
 - intel-spi:
 	- support chips without software sequencer,
 	- add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAl3Kep8ACgkQS1VPR6WN
 FOn9kgf/aKPgU6LR84YpwUKRZ4S+6K1H8SdDUt8v0FYSQ6oaTjF13fApg43WDja5
 Zk0l5tlX7WIvlcRC6XKPhryZTXOKWojW1X8sguPYIZGzo7q82Eyda23jkw1QptWr
 VO9L/tdK4yVUbdtp6VS/FUF31PC0DtDoCzsfBSUgrZP2srFF1BtOJNUgyuDceoxo
 y3hEmINDnkaOvDDl/kbJjdEHG4PV8Vi4k0KE8deLpqlp8GDG1nkTeA1Sim7WjBPA
 ZZOdg9fmGI8H8+umQEnn06H4O95T2+fX+kDMCYo4RbgWyWlGv5TidgRREmC/cSbl
 YEPu6LCQoUZPVEvgolr/8Akf968ZiQ==
 =i15M
 -----END PGP SIGNATURE-----

Merge tag 'spi-nor/for-5.5' into mtd/next

SPI NOR core changes:
- introduce 'struct spi_nor_controller_ops',
- clean the Register Operations methods,
- use dev_dbg insted of dev_err for low level info,
- fix retlen handling in sst_write(),
- fix silent truncations in spi_nor_read and spi_nor_read_raw(),
- fix the clearing of QE bit on lock()/unlock(),
- rework the disabling of the block write protection,
- rework the Quad Enable methods,
- make sure nor->spimem and nor->controller_ops are mutually exclusive,
- set default Quad Enable method for ISSI flashes,
- add support for few flashes.

SPI NOR controller drivers changes:
- intel-spi:
	- support chips without software sequencer,
	- add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
2019-11-17 18:34:01 +01:00
..
aspeed-smc.c mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' 2019-10-23 09:27:21 +03:00
cadence-quadspi.c SPI NOR core changes: 2019-11-17 18:34:01 +01:00
hisi-sfc.c mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' 2019-10-23 09:27:21 +03:00
intel-spi-pci.c mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flash 2019-11-02 12:16:36 +02:00
intel-spi-platform.c mtd: spi-nor: intel-spi: Convert to use SPDX identifier 2019-06-22 14:59:27 +03:00
intel-spi.c mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' 2019-10-23 09:27:21 +03:00
intel-spi.h mtd: spi-nor: intel-spi: Convert to use SPDX identifier 2019-06-22 14:59:27 +03:00
Kconfig mtd: spi-nor: Move m25p80 code in spi-nor.c 2019-08-12 10:54:12 +03:00
Makefile mtd: spi-nor: stm32: remove the driver as it was replaced by spi-stm32-qspi.c 2019-06-07 07:10:38 +03:00
mtk-quadspi.c mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' 2019-10-23 09:27:21 +03:00
nxp-spifi.c mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' 2019-10-23 09:27:21 +03:00
spi-nor.c mtd: spi-nor: Set default Quad Enable method for ISSI flashes 2019-11-11 20:42:55 +02:00