forked from luck/tmp_suning_uos_patched
c431ada45d
When you hot-plug a (root) bridge hierarchy, it may have p2p bridges and devices attached to it that have not been configured by firmware. In this case, we need to configure the devices before starting them. This patch separates device start from device scan so that we can introduce the configuration step in the middle. I kept the existing semantics for pci_scan_bus() since there are a huge number of callers to that function. Also, I have no way of testing the changes I made to the parisc files, so this needs review by those folks. Sorry for the massive cross-post, this touches files in many different places. Signed-off-by: Rajesh Shah <rajesh.shah@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
/*
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* numa.c - Low-level PCI access for NUMA-Q machines
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/nodemask.h>
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#include "pci.h"
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#define BUS2QUAD(global) (mp_bus_id_to_node[global])
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#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
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#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
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#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
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(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
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static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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unsigned long flags;
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if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
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return -EINVAL;
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spin_lock_irqsave(&pci_config_lock, flags);
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outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus));
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switch (len) {
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case 1:
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*value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
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break;
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case 2:
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*value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
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break;
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case 4:
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*value = inl_quad(0xCFC, BUS2QUAD(bus));
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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unsigned long flags;
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if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
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return -EINVAL;
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spin_lock_irqsave(&pci_config_lock, flags);
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outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus));
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switch (len) {
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case 1:
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outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
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break;
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case 2:
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outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
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break;
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case 4:
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outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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#undef PCI_CONF1_MQ_ADDRESS
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static struct pci_raw_ops pci_direct_conf1_mq = {
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.read = pci_conf1_mq_read,
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.write = pci_conf1_mq_write
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};
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static void __devinit pci_fixup_i450nx(struct pci_dev *d)
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{
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/*
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* i450NX -- Find and scan all secondary buses on all PXB's.
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*/
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int pxb, reg;
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u8 busno, suba, subb;
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int quad = BUS2QUAD(d->bus->number);
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printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
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reg = 0xd0;
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for(pxb=0; pxb<2; pxb++) {
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pci_read_config_byte(d, reg++, &busno);
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pci_read_config_byte(d, reg++, &suba);
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pci_read_config_byte(d, reg++, &subb);
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DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
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if (busno)
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pci_scan_bus(QUADLOCAL2BUS(quad,busno), &pci_root_ops, NULL); /* Bus A */
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if (suba < subb)
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pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), &pci_root_ops, NULL); /* Bus B */
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}
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pcibios_last_bus = -1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
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static int __init pci_numa_init(void)
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{
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int quad;
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raw_pci_ops = &pci_direct_conf1_mq;
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if (pcibios_scanned++)
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return 0;
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pci_root_bus = pcibios_scan_root(0);
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if (pci_root_bus)
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pci_bus_add_devices(pci_root_bus);
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if (num_online_nodes() > 1)
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for_each_online_node(quad) {
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if (quad == 0)
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continue;
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printk("Scanning PCI bus %d for quad %d\n",
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QUADLOCAL2BUS(quad,0), quad);
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pci_scan_bus(QUADLOCAL2BUS(quad,0),
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&pci_root_ops, NULL);
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}
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return 0;
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}
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subsys_initcall(pci_numa_init);
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