forked from luck/tmp_suning_uos_patched
a95791efa7
CCI-500 provides 8 event counters which can count any of the supported events independently. The PMU event id is a 9-bit value made of two parts. bits [8:5] - Source port 0x0-0x6 Slave Ports 0x8-0xD Master Ports 0xf Global Events to CCI 0x7,0xe Reserved bits [0:4] - Event code (specific to each type of port) The generic CCI-500 controlling interface remains the same with CCI-400. However there are some differences in the PMU event counters. - No cycle counter - Upto 8 counters(4 in CCI-400) - Each counter area is 64K(4K in CCI400) - The counter0 starts at offset 0x10000 from the base of CCI Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
134 lines
3.7 KiB
Plaintext
134 lines
3.7 KiB
Plaintext
#
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# Bus Devices
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#
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menu "Bus devices"
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config ARM_CCI
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bool
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config ARM_CCI_PMU
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bool
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select ARM_CCI
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config ARM_CCI400_COMMON
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bool
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select ARM_CCI
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config ARM_CCI400_PMU
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bool "ARM CCI400 PMU support"
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depends on (ARM && CPU_V7) || ARM64
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depends on PERF_EVENTS
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select ARM_CCI400_COMMON
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select ARM_CCI_PMU
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help
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Support for PMU events monitoring on the ARM CCI-400 (cache coherent
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interconnect). CCI-400 supports counting events related to the
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connected slave/master interfaces.
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config ARM_CCI400_PORT_CTRL
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bool
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depends on ARM && OF && CPU_V7
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select ARM_CCI400_COMMON
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help
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Low level power management driver for CCI400 cache coherent
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interconnect for ARM platforms.
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config ARM_CCI500_PMU
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bool "ARM CCI500 PMU support"
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default y
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depends on (ARM && CPU_V7) || ARM64
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depends on PERF_EVENTS
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select ARM_CCI_PMU
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help
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Support for PMU events monitoring on the ARM CCI-500 cache coherent
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interconnect. CCI-500 provides 8 independent event counters, which
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can count events pertaining to the slave/master interfaces as well
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as the internal events to the CCI.
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If unsure, say Y
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config ARM_CCN
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bool "ARM CCN driver support"
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depends on ARM || ARM64
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depends on PERF_EVENTS
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help
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PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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interconnect.
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config BRCMSTB_GISB_ARB
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bool "Broadcom STB GISB bus arbiter"
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depends on ARM || MIPS
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help
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Driver for the Broadcom Set Top Box System-on-a-chip internal bus
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arbiter. This driver provides timeout and target abort error handling
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and internal bus master decoding.
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config IMX_WEIM
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bool "Freescale EIM DRIVER"
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depends on ARCH_MXC
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help
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Driver for i.MX WEIM controller.
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The WEIM(Wireless External Interface Module) works like a bus.
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You can attach many different devices on it, such as NOR, onenand.
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config MIPS_CDMM
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bool "MIPS Common Device Memory Map (CDMM) Driver"
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depends on CPU_MIPSR2
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help
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Driver needed for the MIPS Common Device Memory Map bus in MIPS
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cores. This bus is for per-CPU tightly coupled devices such as the
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Fast Debug Channel (FDC).
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For this to work, either your bootloader needs to enable the CDMM
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region at an unused physical address on the boot CPU, or else your
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platform code needs to implement mips_cdmm_phys_base() (see
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asm/cdmm.h).
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config MVEBU_MBUS
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bool
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depends on PLAT_ORION
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help
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Driver needed for the MBus configuration on Marvell EBU SoCs
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(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
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config OMAP_INTERCONNECT
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tristate "OMAP INTERCONNECT DRIVER"
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depends on ARCH_OMAP2PLUS
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help
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Driver to enable OMAP interconnect error handling driver.
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config OMAP_OCP2SCP
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tristate "OMAP OCP2SCP DRIVER"
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depends on ARCH_OMAP2PLUS
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help
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Driver to enable ocp2scp module which transforms ocp interface
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protocol to scp protocol. In OMAP4, USB PHY is connected via
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OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
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OCP2SCP.
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config SIMPLE_PM_BUS
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bool "Simple Power-Managed Bus Driver"
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depends on OF && PM
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depends on ARCH_SHMOBILE || COMPILE_TEST
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help
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Driver for transparent busses that don't need a real driver, but
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where the bus controller is part of a PM domain, or under the control
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of a functional clock, and thus relies on runtime PM for managing
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this PM domain and/or clock.
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An example of such a bus controller is the Renesas Bus State
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Controller (BSC, sometimes called "LBSC within Bus Bridge", or
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"External Bus Interface") as found on several Renesas ARM SoCs.
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config VEXPRESS_CONFIG
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bool "Versatile Express configuration bus"
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default y if ARCH_VEXPRESS
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depends on ARM || ARM64
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depends on OF
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select REGMAP
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help
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Platform configuration infrastructure for the ARM Ltd.
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Versatile Express.
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endmenu
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