forked from luck/tmp_suning_uos_patched
1b948d6cae
The zEC12 machines introduced the local-clearing control for the IDTE and IPTE instruction. If the control is set only the TLB of the local CPU is cleared of entries, either all entries of a single address space for IDTE, or the entry for a single page-table entry for IPTE. Without the local-clearing control the TLB flush is broadcasted to all CPUs in the configuration, which is expensive. The reset of the bit mask of the CPUs that need flushing after a non-local IDTE is tricky. As TLB entries for an address space remain in the TLB even if the address space is detached a new bit field is required to keep track of attached CPUs vs. CPUs in the need of a flush. After a non-local flush with IDTE the bit-field of attached CPUs is copied to the bit-field of CPUs in need of a flush. The ordering of operations on cpu_attach_mask, attach_count and mm_cpumask(mm) is such that an underindication in mm_cpumask(mm) is prevented but an overindication in mm_cpumask(mm) is possible. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
41 lines
907 B
C
41 lines
907 B
C
#ifndef __MMU_H
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#define __MMU_H
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#include <linux/cpumask.h>
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#include <linux/errno.h>
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typedef struct {
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cpumask_t cpu_attach_mask;
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atomic_t attach_count;
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unsigned int flush_mm;
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spinlock_t list_lock;
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struct list_head pgtable_list;
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struct list_head gmap_list;
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unsigned long asce_bits;
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unsigned long asce_limit;
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unsigned long vdso_base;
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/* The mmu context has extended page tables. */
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unsigned int has_pgste:1;
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} mm_context_t;
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#define INIT_MM_CONTEXT(name) \
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.context.list_lock = __SPIN_LOCK_UNLOCKED(name.context.list_lock), \
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.context.pgtable_list = LIST_HEAD_INIT(name.context.pgtable_list), \
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.context.gmap_list = LIST_HEAD_INIT(name.context.gmap_list),
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static inline int tprot(unsigned long addr)
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{
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int rc = -EFAULT;
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asm volatile(
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" tprot 0(%1),0\n"
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"0: ipm %0\n"
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" srl %0,28\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "+d" (rc) : "a" (addr) : "cc");
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return rc;
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}
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#endif
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