forked from luck/tmp_suning_uos_patched
2df36a5dd6
The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we store these as an array of two such registers on the vgic vcpu struct. However, we access them as a single 64-bit value or as a bitmap pointer in the generic vgic code, which breaks BE support. Instead, store them as u64 values on the vgic structure and do the word-swapping in the assembly code, which already handles the byte order for BE systems. Tested-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> |
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.. | ||
arm | ||
assigned-dev.c | ||
async_pf.c | ||
async_pf.h | ||
coalesced_mmio.c | ||
coalesced_mmio.h | ||
eventfd.c | ||
ioapic.c | ||
ioapic.h | ||
iodev.h | ||
iommu.c | ||
irq_comm.c | ||
irqchip.c | ||
Kconfig | ||
kvm_main.c | ||
vfio.c |