forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
132 lines
2.6 KiB
ArmAsm
132 lines
2.6 KiB
ArmAsm
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* First-level interrupt dispatcher for ocelot board.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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/*
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* first level interrupt dispatcher for ocelot board -
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* We check for the timer first, then check PCI ints A and D.
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* Then check for serial IRQ and fall through.
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*/
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.align 5
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NESTED(ocelot_handle_int, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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mfc0 t0, CP0_CAUSE
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mfc0 t2, CP0_STATUS
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and t0, t2
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andi t1, t0, STATUSF_IP2 /* int0 hardware line */
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bnez t1, ll_pri_enet_irq
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andi t1, t0, STATUSF_IP3 /* int1 hardware line */
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bnez t1, ll_sec_enet_irq
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andi t1, t0, STATUSF_IP4 /* int2 hardware line */
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bnez t1, ll_uart_irq
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andi t1, t0, STATUSF_IP5 /* int3 hardware line */
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bnez t1, ll_cpci_irq
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andi t1, t0, STATUSF_IP6 /* int4 hardware line */
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bnez t1, ll_galileo_p0_irq
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andi t1, t0, STATUSF_IP7 /* cpu timer */
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bnez t1, ll_cputimer_irq
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/* now look at the extended interrupts */
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mfc0 t0, CP0_CAUSE
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cfc0 t1, CP0_S1_INTCONTROL
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/* shift the mask 8 bits left to line up the bits */
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sll t2, t1, 8
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and t0, t2
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srl t0, t0, 16
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andi t1, t0, STATUSF_IP8 /* int6 hardware line */
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bnez t1, ll_galileo_p1_irq
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andi t1, t0, STATUSF_IP9 /* int7 hardware line */
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bnez t1, ll_pmc_irq
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andi t1, t0, STATUSF_IP10 /* int8 hardware line */
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bnez t1, ll_cpci_abcd_irq
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andi t1, t0, STATUSF_IP11 /* int9 hardware line */
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bnez t1, ll_testpoint_irq
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.set reorder
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/* wrong alarm or masked ... */
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j spurious_interrupt
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nop
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END(ocelot_handle_int)
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.align 5
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ll_pri_enet_irq:
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li a0, 2
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_sec_enet_irq:
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li a0, 3
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_uart_irq:
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li a0, 4
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_cpci_irq:
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li a0, 5
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_galileo_p0_irq:
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li a0, 6
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_cputimer_irq:
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li a0, 7
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_galileo_p1_irq:
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li a0, 8
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_pmc_irq:
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li a0, 9
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_cpci_abcd_irq:
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li a0, 10
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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ll_testpoint_irq:
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li a0, 11
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move a1, sp
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jal do_IRQ
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j ret_from_irq
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