forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
178 lines
5.6 KiB
C
178 lines
5.6 KiB
C
/*
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* c 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/cache.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/ppcdebug.h>
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#include "i8259.h"
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unsigned char cached_8259[2] = { 0xff, 0xff };
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#define cached_A1 (cached_8259[0])
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#define cached_21 (cached_8259[1])
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static __cacheline_aligned_in_smp DEFINE_SPINLOCK(i8259_lock);
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static int i8259_pic_irq_offset;
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static int i8259_present;
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int i8259_irq(int cpu)
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{
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int irq;
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spin_lock/*_irqsave*/(&i8259_lock/*, flags*/);
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/*
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* Perform an interrupt acknowledge cycle on controller 1
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*/
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outb(0x0C, 0x20);
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irq = inb(0x20) & 7;
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if (irq == 2)
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{
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/*
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* Interrupt is cascaded so perform interrupt
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* acknowledge on controller 2
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*/
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outb(0x0C, 0xA0);
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irq = (inb(0xA0) & 7) + 8;
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}
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else if (irq==7)
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{
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/*
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* This may be a spurious interrupt
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*
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* Read the interrupt status register. If the most
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* significant bit is not set then there is no valid
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* interrupt
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*/
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outb(0x0b, 0x20);
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if(~inb(0x20)&0x80) {
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spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
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return -1;
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}
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}
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spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
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return irq;
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}
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static void i8259_mask_and_ack_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if (irq_nr > 7) {
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cached_A1 |= 1 << (irq_nr-8);
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inb(0xA1); /* DUMMY */
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outb(cached_A1,0xA1);
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outb(0x20,0xA0); /* Non-specific EOI */
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outb(0x20,0x20); /* Non-specific EOI to cascade */
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} else {
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cached_21 |= 1 << irq_nr;
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inb(0x21); /* DUMMY */
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outb(cached_21,0x21);
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outb(0x20,0x20); /* Non-specific EOI */
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}
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_set_irq_mask(int irq_nr)
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{
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outb(cached_A1,0xA1);
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outb(cached_21,0x21);
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}
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static void i8259_mask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if ( irq_nr < 8 )
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cached_21 |= 1 << irq_nr;
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else
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cached_A1 |= 1 << (irq_nr-8);
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_unmask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if ( irq_nr < 8 )
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cached_21 &= ~(1 << irq_nr);
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else
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cached_A1 &= ~(1 << (irq_nr-8));
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_end_irq(unsigned int irq)
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{
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if (!(get_irq_desc(irq)->status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
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get_irq_desc(irq)->action)
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i8259_unmask_irq(irq);
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}
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struct hw_interrupt_type i8259_pic = {
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.typename = " i8259 ",
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.enable = i8259_unmask_irq,
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.disable = i8259_mask_irq,
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.ack = i8259_mask_and_ack_irq,
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.end = i8259_end_irq,
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};
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void __init i8259_init(int offset)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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i8259_pic_irq_offset = offset;
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i8259_present = 1;
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/* init master interrupt controller */
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outb(0x11, 0x20); /* Start init sequence */
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outb(0x00, 0x21); /* Vector base */
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outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0x21); /* Select 8086 mode */
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outb(0xFF, 0x21); /* Mask all */
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/* init slave interrupt controller */
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outb(0x11, 0xA0); /* Start init sequence */
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outb(0x08, 0xA1); /* Vector base */
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outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0xA1); /* Select 8086 mode */
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outb(0xFF, 0xA1); /* Mask all */
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outb(cached_A1, 0xA1);
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outb(cached_21, 0x21);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static int i8259_request_cascade(void)
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{
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if (!i8259_present)
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return -ENODEV;
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request_irq( i8259_pic_irq_offset + 2, no_action, SA_INTERRUPT,
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"82c59 secondary cascade", NULL );
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return 0;
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}
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arch_initcall(i8259_request_cascade);
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