forked from luck/tmp_suning_uos_patched
14b03204c8
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
321 lines
4.8 KiB
ArmAsm
321 lines
4.8 KiB
ArmAsm
/*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <asm/mach/irq.h>
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.section .l1.text
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ENTRY(_sleep_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R1 = W[P0](z);
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BITSET (R1, 3);
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W[P0] = R1.L;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R7 = w[p0](z);
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BITCLR (R7, 3);
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BITCLR (R7, 5);
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w[p0] = R7.L;
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IDLE;
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call _test_pll_locked;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_hibernate_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R1 = W[P0](z);
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BITSET (R1, 8);
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BITCLR (R1, 0);
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BITCLR (R1, 1);
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W[P0] = R1.L;
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SSYNC;
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CLI R2;
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IDLE;
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/* Actually, adding anything may not be necessary...SDRAM contents
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* are lost
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*/
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ENTRY(_deep_sleep)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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CLI R4;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs;
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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call _set_rtc_istat
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 5);
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W[P0] = R0.L;
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call _test_pll_locked;
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SSYNC;
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IDLE;
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call _unset_dram_srfs;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = w[p0](z);
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BITCLR (R0, 3);
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BITCLR (R0, 5);
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BITCLR (R0, 8);
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w[p0] = R0;
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IDLE;
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call _test_pll_locked;
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STI R4;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_sleep_deeper)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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CLI R4;
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P3 = R0;
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P4 = R1;
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P5 = R2;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs; /* Set SDRAM Self Refresh */
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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call _set_rtc_istat;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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R6 = W[P0](z);
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R0.L = 0xF;
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W[P0] = R0.l; /* Set Max VCO to SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R5 = W[P0](z);
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R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
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W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R7 = W[P0](z);
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R1 = 0x6;
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R1 <<= 16;
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R2 = 0x0404(Z);
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R1 = R1|R2;
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R2 = DEPOSIT(R7, R1);
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W[P0] = R2; /* Set Min Core Voltage */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = P3;
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R1 = P4;
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R3 = P5;
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call _set_sic_iwr; /* Set Awake from IDLE */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 3);
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W[P0] = R0.L; /* Turn CCLK OFF */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr; /* Set Awake from IDLE PLL */
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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W[P0]= R7;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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W[P0]= R6; /* Restore CCLK and SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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w[p0] = R5; /* Restore VCO multiplier */
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IDLE;
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call _test_pll_locked;
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call _unset_dram_srfs; /* SDRAM Self Refresh Off */
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STI R4;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_set_dram_srfs)
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/* set the dram to self refresh mode */
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#if defined(CONFIG_BF54x)
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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R3.H = hi(SRREQ);
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R3.L = lo(SRREQ);
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#else
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P0.H = hi(EBIU_SDGCTL);
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P0.L = lo(EBIU_SDGCTL);
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R2 = [P0];
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R3.H = hi(SRFS);
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R3.L = lo(SRFS);
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#endif
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R2 = R2|R3;
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[P0] = R2;
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ssync;
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#if defined(CONFIG_BF54x)
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.LSRR_MODE:
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R2 = [P0];
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CC = BITTST(R2, 4);
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if !CC JUMP .LSRR_MODE;
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#endif
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RTS;
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ENTRY(_unset_dram_srfs)
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/* set the dram out of self refresh mode */
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#if defined(CONFIG_BF54x)
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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R3.H = hi(SRREQ);
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R3.L = lo(SRREQ);
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#else
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P0.H = hi(EBIU_SDGCTL);
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P0.L = lo(EBIU_SDGCTL);
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R2 = [P0];
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R3.H = hi(SRFS);
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R3.L = lo(SRFS);
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#endif
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R3 = ~R3;
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R2 = R2&R3;
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[P0] = R2;
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ssync;
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RTS;
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ENTRY(_set_sic_iwr)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
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P0.H = hi(SIC_IWR0);
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P0.L = lo(SIC_IWR0);
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P1.H = hi(SIC_IWR1);
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P1.L = lo(SIC_IWR1);
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[P1] = R1;
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#if defined(CONFIG_BF54x)
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P1.H = hi(SIC_IWR2);
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P1.L = lo(SIC_IWR2);
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[P1] = R2;
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#endif
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#else
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P0.H = hi(SIC_IWR);
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P0.L = lo(SIC_IWR);
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#endif
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[P0] = R0;
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SSYNC;
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RTS;
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ENTRY(_set_rtc_istat)
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#ifndef CONFIG_BF561
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P0.H = hi(RTC_ISTAT);
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P0.L = lo(RTC_ISTAT);
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w[P0] = R0.L;
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SSYNC;
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#endif
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RTS;
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ENTRY(_test_pll_locked)
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P0.H = hi(PLL_STAT);
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P0.L = lo(PLL_STAT);
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1:
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R0 = W[P0] (Z);
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CC = BITTST(R0,5);
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IF !CC JUMP 1b;
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RTS;
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