forked from luck/tmp_suning_uos_patched
9ddc5b6f18
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
111 lines
3.9 KiB
C
111 lines
3.9 KiB
C
/*
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* Hardware specific macros, defines and structures
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#ifndef HARDWARE_H
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#define HARDWARE_H
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#include <asm/param.h> /* For HZ */
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/*
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* General hardware parameters common to all ISA adapters
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*/
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#define MAX_CARDS 4 /* The maximum number of cards to
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control or probe for. */
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#define SIGNATURE 0x87654321 /* Board reset signature */
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#define SIG_OFFSET 0x1004 /* Where to find signature in shared RAM */
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#define TRACE_OFFSET 0x1008 /* Trace enable word offset in shared RAM */
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#define BUFFER_OFFSET 0x1800 /* Beginning of buffers */
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/* I/O Port parameters */
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#define IOBASE_MIN 0x180 /* Lowest I/O port address */
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#define IOBASE_MAX 0x3C0 /* Highest I/O port address */
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#define IOBASE_OFFSET 0x20 /* Inter-board I/O port gap used during
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probing */
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#define FIFORD_OFFSET 0x0
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#define FIFOWR_OFFSET 0x400
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#define FIFOSTAT_OFFSET 0x1000
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#define RESET_OFFSET 0x2800
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#define PG0_OFFSET 0x3000 /* Offset from I/O Base for Page 0 register */
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#define PG1_OFFSET 0x3400 /* Offset from I/O Base for Page 1 register */
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#define PG2_OFFSET 0x3800 /* Offset from I/O Base for Page 2 register */
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#define PG3_OFFSET 0x3C00 /* Offset from I/O Base for Page 3 register */
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#define FIFO_READ 0 /* FIFO Read register */
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#define FIFO_WRITE 1 /* FIFO Write rgister */
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#define LO_ADDR_PTR 2 /* Extended RAM Low Addr Pointer */
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#define HI_ADDR_PTR 3 /* Extended RAM High Addr Pointer */
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#define NOT_USED_1 4
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#define FIFO_STATUS 5 /* FIFO Status Register */
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#define NOT_USED_2 6
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#define MEM_OFFSET 7
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#define SFT_RESET 10 /* Reset Register */
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#define EXP_BASE 11 /* Shared RAM Base address */
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#define EXP_PAGE0 12 /* Shared RAM Page0 register */
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#define EXP_PAGE1 13 /* Shared RAM Page1 register */
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#define EXP_PAGE2 14 /* Shared RAM Page2 register */
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#define EXP_PAGE3 15 /* Shared RAM Page3 register */
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#define IRQ_SELECT 16 /* IRQ selection register */
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#define MAX_IO_REGS 17 /* Total number of I/O ports */
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/* FIFO register values */
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#define RF_HAS_DATA 0x01 /* fifo has data */
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#define RF_QUART_FULL 0x02 /* fifo quarter full */
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#define RF_HALF_FULL 0x04 /* fifo half full */
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#define RF_NOT_FULL 0x08 /* fifo not full */
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#define WF_HAS_DATA 0x10 /* fifo has data */
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#define WF_QUART_FULL 0x20 /* fifo quarter full */
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#define WF_HALF_FULL 0x40 /* fifo half full */
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#define WF_NOT_FULL 0x80 /* fifo not full */
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/* Shared RAM parameters */
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#define SRAM_MIN 0xC0000 /* Lowest host shared RAM address */
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#define SRAM_MAX 0xEFFFF /* Highest host shared RAM address */
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#define SRAM_PAGESIZE 0x4000 /* Size of one RAM page (16K) */
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/* Shared RAM buffer parameters */
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#define BUFFER_SIZE 0x800 /* The size of a buffer in bytes */
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#define BUFFER_BASE BUFFER_OFFSET /* Offset from start of shared RAM
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where buffer start */
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#define BUFFERS_MAX 16 /* Maximum number of send/receive
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buffers per channel */
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#define HDLC_PROTO 0x01 /* Frame Format for Layer 2 */
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#define BRI_BOARD 0
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#define POTS_BOARD 1
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#define PRI_BOARD 2
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/*
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* Specific hardware parameters for the DataCommute/BRI
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*/
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#define BRI_CHANNELS 2 /* Number of B channels */
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#define BRI_BASEPG_VAL 0x98
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#define BRI_MAGIC 0x60000 /* Magic Number */
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#define BRI_MEMSIZE 0x10000 /* Amount of RAM (64K) */
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#define BRI_PARTNO "72-029"
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#define BRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS;
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/*
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* Specific hardware parameters for the DataCommute/PRI
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*/
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#define PRI_CHANNELS 23 /* Number of B channels */
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#define PRI_BASEPG_VAL 0x88
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#define PRI_MAGIC 0x20000 /* Magic Number */
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#define PRI_MEMSIZE 0x100000 /* Amount of RAM (1M) */
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#define PRI_PARTNO "72-030"
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#define PRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS;
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/*
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* Some handy macros
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*/
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/* Determine if a channel number is valid for the adapter */
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#define IS_VALID_CHANNEL(y,x) ((x>0) && (x <= sc_adapter[y]->channels))
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#endif
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