forked from luck/tmp_suning_uos_patched
bde6f5f59c
Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before entering C3. The performance impact of TLB flush on C3 should not be significant with respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware while in C3 anyways. On a 8 logical CPU system, running make -j2, the number of tlbflush IPIs goes down from 40 per second to ~ 0. Total number of interrupts during the run of this workload was ~1200 per second, which makes it ~3% savings in wakeups. There was no measurable performance or power impact however. [ akpm@linux-foundation.org: symbol export fixes. ] Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
174 lines
4.6 KiB
C
174 lines
4.6 KiB
C
#ifndef _ASM_X86_ACPI_H
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#define _ASM_X86_ACPI_H
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/*
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* Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
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* Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <acpi/pdc_intel.h>
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#include <asm/numa.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#define COMPILER_DEPENDENT_INT64 long long
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#define COMPILER_DEPENDENT_UINT64 unsigned long long
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/*
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* Calling conventions:
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*
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* ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
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* ACPI_EXTERNAL_XFACE - External ACPI interfaces
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* ACPI_INTERNAL_XFACE - Internal ACPI interfaces
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* ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
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*/
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#define ACPI_SYSTEM_XFACE
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#define ACPI_EXTERNAL_XFACE
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#define ACPI_INTERNAL_XFACE
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#define ACPI_INTERNAL_VAR_XFACE
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/* Asm macros */
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#define ACPI_ASM_MACROS
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#define BREAKPOINT3
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#define ACPI_DISABLE_IRQS() local_irq_disable()
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#define ACPI_ENABLE_IRQS() local_irq_enable()
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#define ACPI_FLUSH_CPU_CACHE() wbinvd()
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int __acpi_acquire_global_lock(unsigned int *lock);
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int __acpi_release_global_lock(unsigned int *lock);
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#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
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((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
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#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
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((Acq) = __acpi_release_global_lock(&facs->global_lock))
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/*
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* Math helper asm macros
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*/
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#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
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asm("divl %2;" \
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:"=a"(q32), "=d"(r32) \
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:"r"(d32), \
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"0"(n_lo), "1"(n_hi))
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#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
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asm("shrl $1,%2 ;" \
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"rcrl $1,%3;" \
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:"=r"(n_hi), "=r"(n_lo) \
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:"0"(n_hi), "1"(n_lo))
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#ifdef CONFIG_ACPI
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extern int acpi_lapic;
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extern int acpi_ioapic;
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extern int acpi_noirq;
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extern int acpi_strict;
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extern int acpi_disabled;
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extern int acpi_ht;
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extern int acpi_pci_disabled;
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extern int acpi_skip_timer_override;
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extern int acpi_use_timer_override;
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static inline void disable_acpi(void)
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{
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acpi_disabled = 1;
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acpi_ht = 0;
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acpi_pci_disabled = 1;
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acpi_noirq = 1;
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}
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/* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */
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#define FIX_ACPI_PAGES 4
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extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
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static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
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static inline void acpi_disable_pci(void)
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{
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acpi_pci_disabled = 1;
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acpi_noirq_set();
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}
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extern int acpi_irq_balance_set(char *str);
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/* routines for saving/restoring kernel state */
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extern int acpi_save_state_mem(void);
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extern void acpi_restore_state_mem(void);
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extern unsigned long acpi_wakeup_address;
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/* early initialization routine */
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extern void acpi_reserve_bootmem(void);
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/*
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* Check if the CPU can handle C2 and deeper
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*/
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static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
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{
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/*
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* Early models (<=5) of AMD Opterons are not supposed to go into
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* C2 state.
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*
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* Steppings 0x0A and later are good
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*/
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if (boot_cpu_data.x86 == 0x0F &&
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boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86_model <= 0x05 &&
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boot_cpu_data.x86_mask < 0x0A)
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return 1;
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else
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return max_cstate;
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}
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#else /* !CONFIG_ACPI */
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#define acpi_lapic 0
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#define acpi_ioapic 0
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static inline void acpi_noirq_set(void) { }
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static inline void acpi_disable_pci(void) { }
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static inline void disable_acpi(void) { }
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#endif /* !CONFIG_ACPI */
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#define ARCH_HAS_POWER_INIT 1
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struct bootnode;
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#ifdef CONFIG_ACPI_NUMA
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extern int acpi_numa;
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extern int acpi_scan_nodes(unsigned long start, unsigned long end);
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#ifdef CONFIG_X86_64
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# define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
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#endif
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extern void acpi_fake_nodes(const struct bootnode *fake_nodes,
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int num_nodes);
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#else
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static inline void acpi_fake_nodes(const struct bootnode *fake_nodes,
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int num_nodes)
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{
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}
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#endif
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#define acpi_unlazy_tlb(x) leave_mm(x)
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#endif /*__X86_ASM_ACPI_H*/
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