forked from luck/tmp_suning_uos_patched
1bbe0ecc2a
This patch adds support for initializing the MACsec engine found within some Microsemi PHYs. The engine is initialized in a passthrough mode and does not modify any incoming or outgoing packet. But thanks to this it now can be configured to perform MACsec transformations on packets, which will be supported by a future patch. The MACsec read and write functions are wrapped into two versions: one called during the init phase, and the other one later on. This is because the init functions in the Microsemi PHY driver are called while the MDIO bus lock is taken. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
160 lines
7.5 KiB
C
160 lines
7.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_LINE_MAC_H_
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#define _MSCC_OCELOT_LINE_MAC_H_
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#define MSCC_MAC_CFG_ENA_CFG 0x00
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#define MSCC_MAC_CFG_MODE_CFG 0x01
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#define MSCC_MAC_CFG_MAXLEN_CFG 0x02
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#define MSCC_MAC_CFG_NUM_TAGS_CFG 0x03
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#define MSCC_MAC_CFG_TAGS_CFG 0x04
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#define MSCC_MAC_CFG_ADV_CHK_CFG 0x07
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#define MSCC_MAC_CFG_LFS_CFG 0x08
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#define MSCC_MAC_CFG_LB_CFG 0x09
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#define MSCC_MAC_CFG_PKTINF_CFG 0x0a
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL 0x0b
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2 0x0c
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL 0x0d
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#define MSCC_MAC_PAUSE_CFG_STATE 0x0e
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#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_LSB 0x0f
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#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_MSB 0x10
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#define MSCC_MAC_STATUS_RX_LANE_STICKY_0 0x11
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#define MSCC_MAC_STATUS_RX_LANE_STICKY_1 0x12
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#define MSCC_MAC_STATUS_TX_MONITOR_STICKY 0x13
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#define MSCC_MAC_STATUS_TX_MONITOR_STICKY_MASK 0x14
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#define MSCC_MAC_STATUS_STICKY 0x15
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#define MSCC_MAC_STATUS_STICKY_MASK 0x16
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#define MSCC_MAC_STATS_32BIT_RX_HIH_CKSM_ERR_CNT 0x17
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#define MSCC_MAC_STATS_32BIT_RX_XGMII_PROT_ERR_CNT 0x18
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#define MSCC_MAC_STATS_32BIT_RX_SYMBOL_ERR_CNT 0x19
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#define MSCC_MAC_STATS_32BIT_RX_PAUSE_CNT 0x1a
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#define MSCC_MAC_STATS_32BIT_RX_UNSUP_OPCODE_CNT 0x1b
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#define MSCC_MAC_STATS_32BIT_RX_UC_CNT 0x1c
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#define MSCC_MAC_STATS_32BIT_RX_MC_CNT 0x1d
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#define MSCC_MAC_STATS_32BIT_RX_BC_CNT 0x1e
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#define MSCC_MAC_STATS_32BIT_RX_CRC_ERR_CNT 0x1f
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#define MSCC_MAC_STATS_32BIT_RX_UNDERSIZE_CNT 0x20
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#define MSCC_MAC_STATS_32BIT_RX_FRAGMENTS_CNT 0x21
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#define MSCC_MAC_STATS_32BIT_RX_IN_RANGE_LEN_ERR_CNT 0x22
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#define MSCC_MAC_STATS_32BIT_RX_OUT_OF_RANGE_LEN_ERR_CNT 0x23
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#define MSCC_MAC_STATS_32BIT_RX_OVERSIZE_CNT 0x24
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#define MSCC_MAC_STATS_32BIT_RX_JABBERS_CNT 0x25
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#define MSCC_MAC_STATS_32BIT_RX_SIZE64_CNT 0x26
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#define MSCC_MAC_STATS_32BIT_RX_SIZE65TO127_CNT 0x27
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#define MSCC_MAC_STATS_32BIT_RX_SIZE128TO255_CNT 0x28
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#define MSCC_MAC_STATS_32BIT_RX_SIZE256TO511_CNT 0x29
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#define MSCC_MAC_STATS_32BIT_RX_SIZE512TO1023_CNT 0x2a
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#define MSCC_MAC_STATS_32BIT_RX_SIZE1024TO1518_CNT 0x2b
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#define MSCC_MAC_STATS_32BIT_RX_SIZE1519TOMAX_CNT 0x2c
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#define MSCC_MAC_STATS_32BIT_RX_IPG_SHRINK_CNT 0x2d
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#define MSCC_MAC_STATS_32BIT_TX_PAUSE_CNT 0x2e
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#define MSCC_MAC_STATS_32BIT_TX_UC_CNT 0x2f
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#define MSCC_MAC_STATS_32BIT_TX_MC_CNT 0x30
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#define MSCC_MAC_STATS_32BIT_TX_BC_CNT 0x31
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#define MSCC_MAC_STATS_32BIT_TX_SIZE64_CNT 0x32
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#define MSCC_MAC_STATS_32BIT_TX_SIZE65TO127_CNT 0x33
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#define MSCC_MAC_STATS_32BIT_TX_SIZE128TO255_CNT 0x34
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#define MSCC_MAC_STATS_32BIT_TX_SIZE256TO511_CNT 0x35
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#define MSCC_MAC_STATS_32BIT_TX_SIZE512TO1023_CNT 0x36
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#define MSCC_MAC_STATS_32BIT_TX_SIZE1024TO1518_CNT 0x37
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#define MSCC_MAC_STATS_32BIT_TX_SIZE1519TOMAX_CNT 0x38
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#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_CNT 0x39
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#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_MSB_CNT 0x3a
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#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_CNT 0x3b
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#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_MSB_CNT 0x3c
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#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_CNT 0x3d
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#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_MSB_CNT 0x3e
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#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_CNT 0x3f
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#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_MSB_CNT 0x40
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#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_CNT 0x41
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#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_MSB_CNT 0x42
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#define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0)
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#define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4)
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#define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8)
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#define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12)
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#define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16)
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#define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20)
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#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x) ((x) << 20)
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#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M GENMASK(29, 20)
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#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16)
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#define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES BIT(14)
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#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG(x) ((x) << 10)
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#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M GENMASK(12, 10)
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#define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG BIT(6)
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#define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA BIT(4)
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#define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK BIT(2)
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#define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS BIT(1)
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#define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC BIT(0)
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#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
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#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(x) (x)
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#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M GENMASK(15, 0)
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#define MSCC_MAC_CFG_TAGS_CFG_RSZ 0x4
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#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID(x) ((x) << 16)
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#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
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#define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA BIT(4)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
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#define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
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#define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX BIT(8)
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#define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX BIT(4)
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#define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA BIT(3)
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#define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT BIT(2)
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#define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS BIT(1)
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#define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA BIT(0)
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#define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA BIT(4)
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#define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA BIT(0)
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#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA BIT(0)
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#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA BIT(4)
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#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA BIT(8)
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#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA BIT(12)
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#define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA BIT(16)
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#define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA BIT(20)
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#define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA BIT(24)
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#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING BIT(25)
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#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING BIT(26)
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#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE BIT(27)
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#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(x) ((x) << 28)
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#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M GENMASK(30, 28)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(x) ((x) << 16)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M GENMASK(31, 16)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW BIT(12)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA BIT(8)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE BIT(4)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME BIT(2)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(x) (x)
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#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M GENMASK(1, 0)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA BIT(16)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE BIT(20)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA BIT(12)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA BIT(8)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA BIT(4)
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#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE BIT(0)
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#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)
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#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)
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#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
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#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
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#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
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#endif /* _MSCC_OCELOT_LINE_MAC_H_ */
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