forked from luck/tmp_suning_uos_patched
3587c26090
Commit 5c31252c4a ("pwm: Add the pwm_is_enabled() helper") introduced
a new function to test whether a PWM device is enabled or not without
manipulating PWM internal fields.
Hiding this is necessary if we want to smoothly move to the atomic PWM
config approach without impacting PWM drivers. Fix this driver to use
pwm_is_enabled() instead of directly accessing the ->flags field.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
275 lines
6.6 KiB
C
275 lines
6.6 KiB
C
/*
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* R-Car PWM Timer driver
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define RCAR_PWM_MAX_DIVISION 24
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#define RCAR_PWM_MAX_CYCLE 1023
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#define RCAR_PWMCR 0x00
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#define RCAR_PWMCR_CC0_MASK 0x000f0000
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#define RCAR_PWMCR_CC0_SHIFT 16
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#define RCAR_PWMCR_CCMD BIT(15)
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#define RCAR_PWMCR_SYNC BIT(11)
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#define RCAR_PWMCR_SS0 BIT(4)
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#define RCAR_PWMCR_EN0 BIT(0)
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#define RCAR_PWMCNT 0x04
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#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
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#define RCAR_PWMCNT_CYC0_SHIFT 16
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#define RCAR_PWMCNT_PH0_MASK 0x000003ff
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#define RCAR_PWMCNT_PH0_SHIFT 0
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struct rcar_pwm_chip {
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struct pwm_chip chip;
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void __iomem *base;
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struct clk *clk;
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};
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static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct rcar_pwm_chip, chip);
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}
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static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
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unsigned int offset)
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{
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writel(data, rp->base + offset);
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}
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static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
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{
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return readl(rp->base + offset);
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}
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static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
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unsigned int offset)
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{
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u32 value;
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value = rcar_pwm_read(rp, offset);
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value &= ~mask;
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value |= data & mask;
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rcar_pwm_write(rp, value, offset);
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}
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static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
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{
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unsigned long clk_rate = clk_get_rate(rp->clk);
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unsigned long long max; /* max cycle / nanoseconds */
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unsigned int div;
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if (clk_rate == 0)
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return -EINVAL;
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for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) {
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max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE *
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(1 << div);
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do_div(max, clk_rate);
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if (period_ns <= max)
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break;
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}
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return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
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}
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static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
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unsigned int div)
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{
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u32 value;
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value = rcar_pwm_read(rp, RCAR_PWMCR);
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value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
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if (div & 1)
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value |= RCAR_PWMCR_CCMD;
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div >>= 1;
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value |= div << RCAR_PWMCR_CC0_SHIFT;
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rcar_pwm_write(rp, value, RCAR_PWMCR);
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}
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static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
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int period_ns)
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{
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unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
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unsigned long clk_rate = clk_get_rate(rp->clk);
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u32 cyc, ph;
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one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
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do_div(one_cycle, clk_rate);
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tmp = period_ns * 100ULL;
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do_div(tmp, one_cycle);
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cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
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tmp = duty_ns * 100ULL;
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do_div(tmp, one_cycle);
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ph = tmp & RCAR_PWMCNT_PH0_MASK;
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/* Avoid prohibited setting */
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if (cyc == 0 || ph == 0)
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return -EINVAL;
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rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
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return 0;
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}
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static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
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return clk_prepare_enable(rp->clk);
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}
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static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
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clk_disable_unprepare(rp->clk);
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}
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static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
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int div, ret;
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div = rcar_pwm_get_clock_division(rp, period_ns);
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if (div < 0)
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return div;
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/* Let the core driver set pwm->period if disabled and duty_ns == 0 */
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if (!pwm_is_enabled(pwm) && !duty_ns)
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return 0;
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rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
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ret = rcar_pwm_set_counter(rp, div, duty_ns, period_ns);
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if (!ret)
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rcar_pwm_set_clock_control(rp, div);
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/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
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rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
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return ret;
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}
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static int rcar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
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u32 value;
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/* Don't enable the PWM device if CYC0 or PH0 is 0 */
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value = rcar_pwm_read(rp, RCAR_PWMCNT);
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if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
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(value & RCAR_PWMCNT_PH0_MASK) == 0)
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return -EINVAL;
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rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
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return 0;
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}
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static void rcar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
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rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
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}
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static const struct pwm_ops rcar_pwm_ops = {
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.request = rcar_pwm_request,
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.free = rcar_pwm_free,
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.config = rcar_pwm_config,
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.enable = rcar_pwm_enable,
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.disable = rcar_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int rcar_pwm_probe(struct platform_device *pdev)
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{
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struct rcar_pwm_chip *rcar_pwm;
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struct resource *res;
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int ret;
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rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
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if (rcar_pwm == NULL)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rcar_pwm->base))
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return PTR_ERR(rcar_pwm->base);
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rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(rcar_pwm->clk)) {
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dev_err(&pdev->dev, "cannot get clock\n");
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return PTR_ERR(rcar_pwm->clk);
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}
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platform_set_drvdata(pdev, rcar_pwm);
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rcar_pwm->chip.dev = &pdev->dev;
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rcar_pwm->chip.ops = &rcar_pwm_ops;
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rcar_pwm->chip.base = -1;
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rcar_pwm->chip.npwm = 1;
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ret = pwmchip_add(&rcar_pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
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return ret;
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}
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pm_runtime_enable(&pdev->dev);
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return 0;
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}
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static int rcar_pwm_remove(struct platform_device *pdev)
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{
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struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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return pwmchip_remove(&rcar_pwm->chip);
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}
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static const struct of_device_id rcar_pwm_of_table[] = {
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{ .compatible = "renesas,pwm-rcar", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
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static struct platform_driver rcar_pwm_driver = {
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.probe = rcar_pwm_probe,
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.remove = rcar_pwm_remove,
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.driver = {
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.name = "pwm-rcar",
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.of_match_table = of_match_ptr(rcar_pwm_of_table),
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}
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};
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module_platform_driver(rcar_pwm_driver);
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MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
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MODULE_DESCRIPTION("Renesas PWM Timer Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:pwm-rcar");
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