kernel_optimize_test/include/dt-bindings
Lucas Stach 581098969c clk: imx8mq: remove SYS PLL 1/2 clock gates
[ Upstream commit c586f53ae159c6c1390f093a1ec94baef2df9f3a ]

Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a5 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-14 16:56:20 +02:00
..
arm
bus
clk
clock
display
dma
firmware/imx
gce
gpio
i2c
iio
input
interconnect
interrupt-controller
leds
mailbox
media
memory
mfd
mips
mux
net
phy
pinctrl
pmu
power
pwm
regulator
reset
reset-controller
soc
sound
spmi
thermal
usb