forked from luck/tmp_suning_uos_patched
f2c4db1bd8
Going primarily by: https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors with additional information gleaned from other related pages; notably: - Bonnell shrink was called Saltwell - Moorefield is the Merriefield refresh which makes it Airmont The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE for i in `git grep -l FAM6_ATOM` ; do sed -i -e 's/ATOM_PINEVIEW/ATOM_BONNELL/g' \ -e 's/ATOM_LINCROFT/ATOM_BONNELL_MID/' \ -e 's/ATOM_PENWELL/ATOM_SALTWELL_MID/g' \ -e 's/ATOM_CLOVERVIEW/ATOM_SALTWELL_TABLET/g' \ -e 's/ATOM_CEDARVIEW/ATOM_SALTWELL/g' \ -e 's/ATOM_SILVERMONT1/ATOM_SILVERMONT/g' \ -e 's/ATOM_SILVERMONT2/ATOM_SILVERMONT_X/g' \ -e 's/ATOM_MERRIFIELD/ATOM_SILVERMONT_MID/g' \ -e 's/ATOM_MOOREFIELD/ATOM_AIRMONT_MID/g' \ -e 's/ATOM_DENVERTON/ATOM_GOLDMONT_X/g' \ -e 's/ATOM_GEMINI_LAKE/ATOM_GOLDMONT_PLUS/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: dave.hansen@linux.intel.com Cc: len.brown@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
80 lines
1.7 KiB
C
80 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel MID platform PM support
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*
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* Copyright (C) 2016, Intel Corporation
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*
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/intel-mid.h>
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#include "pci.h"
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static bool mid_pci_power_manageable(struct pci_dev *dev)
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{
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return true;
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}
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static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
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{
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return intel_mid_pci_set_power_state(pdev, state);
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}
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static pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
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{
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return intel_mid_pci_get_power_state(pdev);
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}
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static pci_power_t mid_pci_choose_state(struct pci_dev *pdev)
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{
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return PCI_D3hot;
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}
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static int mid_pci_wakeup(struct pci_dev *dev, bool enable)
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{
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return 0;
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}
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static bool mid_pci_need_resume(struct pci_dev *dev)
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{
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return false;
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}
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static const struct pci_platform_pm_ops mid_pci_platform_pm = {
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.is_manageable = mid_pci_power_manageable,
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.set_state = mid_pci_set_power_state,
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.get_state = mid_pci_get_power_state,
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.choose_state = mid_pci_choose_state,
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.set_wakeup = mid_pci_wakeup,
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.need_resume = mid_pci_need_resume,
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};
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#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
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/*
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* This table should be in sync with the one in
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* arch/x86/platform/intel-mid/pwr.c.
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*/
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static const struct x86_cpu_id lpss_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_SALTWELL_MID),
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ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID),
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{}
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};
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static int __init mid_pci_init(void)
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{
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const struct x86_cpu_id *id;
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id = x86_match_cpu(lpss_cpu_ids);
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if (id)
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pci_set_platform_pm(&mid_pci_platform_pm);
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return 0;
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}
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arch_initcall(mid_pci_init);
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