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Paul Cercueil 3860dc599b clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
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drivers clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL 2020-10-13 20:04:50 -07:00
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Linux kernel
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