Paul Cercueil 3860dc599b clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL ... CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2020-10-13 20:04:50 -07:00
..
cgu.c	clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL	2020-10-13 20:04:50 -07:00
cgu.h	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	2020-05-28 16:13:15 -07:00
jz4725b-cgu.c	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	2020-05-28 16:13:15 -07:00
jz4740-cgu.c	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	2020-05-28 16:13:15 -07:00
jz4770-cgu.c	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	2020-05-28 16:13:15 -07:00
jz4780-cgu.c	clk: JZ4780: Reformat the code to align it.	2020-07-27 18:18:14 -07:00
Kconfig	clk: Ingenic: Add CGU driver for X1830.	2020-05-28 16:13:19 -07:00
Makefile	clk: Ingenic: Add CGU driver for X1830.	2020-05-28 16:13:19 -07:00
pm.c	clk: ingenic: Handle setting the Low-Power Mode bit	2019-06-25 15:43:15 -07:00
pm.h	clk: ingenic: Handle setting the Low-Power Mode bit	2019-06-25 15:43:15 -07:00
tcu.c	clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused	2020-05-28 16:47:02 -07:00
x1000-cgu.c	clk: X1000: Add support for calculat REFCLK of USB PHY.	2020-07-27 18:18:14 -07:00
x1830-cgu.c	clk: Ingenic: Add RTC related clocks for Ingenic SoCs.	2020-07-27 18:17:52 -07:00