forked from luck/tmp_suning_uos_patched
724ce5ee15
The hardware team changed some things that were taken as being common to all ns9xxx processors up to now. This patch addresses: - irqs: s/IRQ_/IRQ_NS9360_/ - system module registers: some registers are still general, their definition lives now in include/asm-arm/arch-ns9xxx/regs-sys-common.h. The ns9360 specific ones are in .../regs-sys-ns9360.h As a result ns9360_systemclock cannot be static inline any more as its definition needs regs-sys-ns9360.h. This becomes a real problem when adding support for ns9215 as this will need regs-sys-ns9215.h and including both files will not work. For the same reason ns9360_reset() is now non-inline and gpio functions live in their own file. - register mapping: s/ns9xxx_map_io/ns9360_map_io/ - timer registers: move time.c to time-ns9360.c; s/ns9xxx_timer/ns9360_timer/ Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
160 lines
3.7 KiB
C
160 lines
3.7 KiB
C
/*
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* arch/arm/mach-ns9xxx/board-a9m9750dev.c
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*
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* Copyright (C) 2006,2007 by Digi International Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/irq.h>
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#include <asm/mach/map.h>
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#include <asm/gpio.h>
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#include <asm/arch-ns9xxx/board.h>
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#include <asm/arch-ns9xxx/processor-ns9360.h>
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#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
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#include <asm/arch-ns9xxx/regs-mem.h>
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#include <asm/arch-ns9xxx/regs-bbu.h>
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#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
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#include "board-a9m9750dev.h"
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static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
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{ /* FPGA on CS0 */
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.virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
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.pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
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.length = NS9XXX_CS0STAT_LENGTH,
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.type = MT_DEVICE,
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},
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};
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void __init board_a9m9750dev_map_io(void)
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{
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iotable_init(board_a9m9750dev_io_desc,
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ARRAY_SIZE(board_a9m9750dev_io_desc));
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}
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static void a9m9750dev_fpga_ack_irq(unsigned int irq)
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{
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/* nothing */
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}
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static void a9m9750dev_fpga_mask_irq(unsigned int irq)
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{
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u8 ier;
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ier = __raw_readb(FPGA_IER);
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ier &= ~(1 << (irq - FPGA_IRQ(0)));
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__raw_writeb(ier, FPGA_IER);
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}
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static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
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{
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a9m9750dev_fpga_mask_irq(irq);
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a9m9750dev_fpga_ack_irq(irq);
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}
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static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
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{
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u8 ier;
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ier = __raw_readb(FPGA_IER);
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ier |= 1 << (irq - FPGA_IRQ(0));
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__raw_writeb(ier, FPGA_IER);
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}
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static struct irq_chip a9m9750dev_fpga_chip = {
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.ack = a9m9750dev_fpga_ack_irq,
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.mask = a9m9750dev_fpga_mask_irq,
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.mask_ack = a9m9750dev_fpga_maskack_irq,
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.unmask = a9m9750dev_fpga_unmask_irq,
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};
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static void a9m9750dev_fpga_demux_handler(unsigned int irq,
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struct irq_desc *desc)
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{
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u8 stat = __raw_readb(FPGA_ISR);
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desc->chip->mask_ack(irq);
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while (stat != 0) {
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int irqno = fls(stat) - 1;
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struct irq_desc *fpgadesc;
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stat &= ~(1 << irqno);
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fpgadesc = irq_desc + FPGA_IRQ(irqno);
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desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
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}
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desc->chip->unmask(irq);
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}
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void __init board_a9m9750dev_init_irq(void)
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{
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u32 eic;
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int i;
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if (gpio_request(11, "board a9m9750dev extirq2") == 0)
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ns9360_gpio_configure(11, 0, 1);
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else
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printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
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__func__);
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for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
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set_irq_chip(i, &a9m9750dev_fpga_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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/* IRQ_NS9XXX_EXT2: level sensitive + active low */
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eic = __raw_readl(SYS_EIC(2));
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REGSET(eic, SYS_EIC, PLTY, AL);
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REGSET(eic, SYS_EIC, LVEDG, LEVEL);
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__raw_writel(eic, SYS_EIC(2));
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set_irq_chained_handler(IRQ_NS9XXX_EXT2,
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a9m9750dev_fpga_demux_handler);
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}
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void __init board_a9m9750dev_init_machine(void)
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{
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u32 reg;
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/* setup static CS0: memory base ... */
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reg = __raw_readl(SYS_SMCSSMB(0));
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REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
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__raw_writel(reg, SYS_SMCSSMB(0));
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/* ... and mask */
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reg = __raw_readl(SYS_SMCSSMM(0));
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REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
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REGSET(reg, SYS_SMCSSMM, CSEx, EN);
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__raw_writel(reg, SYS_SMCSSMM(0));
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/* setup static CS0: memory configuration */
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reg = __raw_readl(MEM_SMC(0));
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REGSET(reg, MEM_SMC, PSMC, OFF);
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REGSET(reg, MEM_SMC, BSMC, OFF);
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REGSET(reg, MEM_SMC, EW, OFF);
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REGSET(reg, MEM_SMC, PB, 1);
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REGSET(reg, MEM_SMC, PC, AL);
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REGSET(reg, MEM_SMC, PM, DIS);
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REGSET(reg, MEM_SMC, MW, 8);
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__raw_writel(reg, MEM_SMC(0));
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/* setup static CS0: timing */
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__raw_writel(0x2, MEM_SMWED(0));
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__raw_writel(0x2, MEM_SMOED(0));
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__raw_writel(0x6, MEM_SMRD(0));
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__raw_writel(0x6, MEM_SMWD(0));
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}
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