forked from luck/tmp_suning_uos_patched
928bea9648
We currently enable PCI bridges after scanning a bus and assigning resources. This is often done in arch code. This patch changes this so we don't enable a bridge until necessary, i.e., until we enable a PCI device behind the bridge. We do this in the generic pci_enable_device() path, so this also removes the arch-specific code to enable bridges. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* cardbus.c -- 16-bit PCMCIA core support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* (C) 1999 David A. Hinds
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*/
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/*
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* Cardbus handling has been re-written to be more of a PCI bridge thing,
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* and the PCI code basically does all the resource handling.
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*
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* Linus, Jan 2000
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <pcmcia/ss.h>
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static void cardbus_config_irq_and_cls(struct pci_bus *bus, int irq)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u8 irq_pin;
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/*
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* Since there is only one interrupt available to
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* CardBus devices, all devices downstream of this
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* device must be using this IRQ.
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*/
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
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if (irq_pin) {
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dev->irq = irq;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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}
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/*
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* Some controllers transfer very slowly with 0 CLS.
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* Configure it. This may fail as CLS configuration
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* is mandatory only for MWI.
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*/
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pci_set_cacheline_size(dev);
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if (dev->subordinate)
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cardbus_config_irq_and_cls(dev->subordinate, irq);
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}
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}
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/**
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* cb_alloc() - add CardBus device
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* @s: the pcmcia_socket where the CardBus device is located
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*
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* cb_alloc() allocates the kernel data structures for a Cardbus device
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* and handles the lowest level PCI device setup issues.
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*/
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int __ref cb_alloc(struct pcmcia_socket *s)
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{
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struct pci_bus *bus = s->cb_dev->subordinate;
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struct pci_dev *dev;
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unsigned int max, pass;
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s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
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pci_fixup_cardbus(bus);
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max = bus->busn_res.start;
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for (pass = 0; pass < 2; pass++)
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
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dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
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max = pci_scan_bridge(bus, dev, max, pass);
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/*
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* Size all resources below the CardBus controller.
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*/
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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cardbus_config_irq_and_cls(bus, s->pci_irq);
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/* socket specific tune function */
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if (s->tune_bridge)
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s->tune_bridge(s, bus);
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pci_bus_add_devices(bus);
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return 0;
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}
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/**
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* cb_free() - remove CardBus device
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* @s: the pcmcia_socket where the CardBus device was located
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*
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* cb_free() handles the lowest level PCI device cleanup.
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*/
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void cb_free(struct pcmcia_socket *s)
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{
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struct pci_dev *bridge, *dev, *tmp;
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struct pci_bus *bus;
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bridge = s->cb_dev;
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if (!bridge)
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return;
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bus = bridge->subordinate;
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if (!bus)
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return;
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list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list)
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pci_stop_and_remove_bus_device(dev);
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}
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