forked from luck/tmp_suning_uos_patched
1365 lines
32 KiB
C
1365 lines
32 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
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* Copyright (C) 1995, 1996 Paul M. Antoine
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* Copyright (C) 1998 Ulf Carlsson
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 01 MIPS Technologies, Inc.
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* Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/bootmem.h>
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#include <asm/bootinfo.h>
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#include <asm/branch.h>
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#include <asm/break.h>
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#include <asm/cpu.h>
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/module.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include <asm/sections.h>
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#include <asm/system.h>
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#include <asm/tlbdebug.h>
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#include <asm/traps.h>
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#include <asm/uaccess.h>
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#include <asm/mmu_context.h>
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#include <asm/watch.h>
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#include <asm/types.h>
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extern asmlinkage void handle_tlbm(void);
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extern asmlinkage void handle_tlbl(void);
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extern asmlinkage void handle_tlbs(void);
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extern asmlinkage void handle_adel(void);
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extern asmlinkage void handle_ades(void);
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extern asmlinkage void handle_ibe(void);
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extern asmlinkage void handle_dbe(void);
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extern asmlinkage void handle_sys(void);
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extern asmlinkage void handle_bp(void);
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extern asmlinkage void handle_ri(void);
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extern asmlinkage void handle_cpu(void);
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extern asmlinkage void handle_ov(void);
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extern asmlinkage void handle_tr(void);
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extern asmlinkage void handle_fpe(void);
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extern asmlinkage void handle_mdmx(void);
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extern asmlinkage void handle_watch(void);
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extern asmlinkage void handle_mt(void);
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extern asmlinkage void handle_dsp(void);
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extern asmlinkage void handle_mcheck(void);
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extern asmlinkage void handle_reserved(void);
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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struct mips_fpu_soft_struct *ctx);
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void (*board_be_init)(void);
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int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
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void (*board_nmi_handler_setup)(void);
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void (*board_ejtag_handler_setup)(void);
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void (*board_bind_eic_interrupt)(int irq, int regset);
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/*
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* These constant is for searching for possible module text segments.
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* MODULE_RANGE is a guess of how much space is likely to be vmalloced.
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*/
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#define MODULE_RANGE (8*1024*1024)
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/*
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* This routine abuses get_user()/put_user() to reference pointers
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* with at least a bit of error checking ...
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*/
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void show_stack(struct task_struct *task, unsigned long *sp)
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{
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const int field = 2 * sizeof(unsigned long);
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long stackdata;
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int i;
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if (!sp) {
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if (task && task != current)
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sp = (unsigned long *) task->thread.reg29;
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else
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sp = (unsigned long *) &sp;
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}
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printk("Stack :");
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i = 0;
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while ((unsigned long) sp & (PAGE_SIZE - 1)) {
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if (i && ((i % (64 / field)) == 0))
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printk("\n ");
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if (i > 39) {
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printk(" ...");
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break;
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}
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if (__get_user(stackdata, sp++)) {
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printk(" (Bad stack address)");
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break;
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}
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printk(" %0*lx", field, stackdata);
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i++;
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}
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printk("\n");
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}
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void show_trace(struct task_struct *task, unsigned long *stack)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned long addr;
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if (!stack) {
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if (task && task != current)
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stack = (unsigned long *) task->thread.reg29;
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else
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stack = (unsigned long *) &stack;
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}
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printk("Call Trace:");
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#ifdef CONFIG_KALLSYMS
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printk("\n");
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#endif
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while (!kstack_end(stack)) {
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addr = *stack++;
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if (__kernel_text_address(addr)) {
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printk(" [<%0*lx>] ", field, addr);
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print_symbol("%s\n", addr);
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}
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}
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printk("\n");
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}
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/*
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* The architecture-independent dump_stack generator
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*/
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void dump_stack(void)
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{
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unsigned long stack;
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show_trace(current, &stack);
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}
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EXPORT_SYMBOL(dump_stack);
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void show_code(unsigned int *pc)
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{
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long i;
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printk("\nCode:");
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for(i = -3 ; i < 6 ; i++) {
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unsigned int insn;
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if (__get_user(insn, pc + i)) {
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printk(" (Bad address in epc)\n");
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break;
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}
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printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
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}
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}
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void show_regs(struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int cause = regs->cp0_cause;
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int i;
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printk("Cpu %d\n", smp_processor_id());
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printk("$%2d :", i);
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if (i == 0)
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printk(" %0*lx", field, 0UL);
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else if (i == 26 || i == 27)
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printk(" %*s", field, "");
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else
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printk(" %0*lx", field, regs->regs[i]);
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i++;
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if ((i % 4) == 0)
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printk("\n");
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}
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printk("Hi : %0*lx\n", field, regs->hi);
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printk("Lo : %0*lx\n", field, regs->lo);
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/*
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* Saved cp0 registers
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*/
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printk("epc : %0*lx ", field, regs->cp0_epc);
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print_symbol("%s ", regs->cp0_epc);
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printk(" %s\n", print_tainted());
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printk("ra : %0*lx ", field, regs->regs[31]);
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print_symbol("%s\n", regs->regs[31]);
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printk("Status: %08x ", (uint32_t) regs->cp0_status);
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if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
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if (regs->cp0_status & ST0_KUO)
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printk("KUo ");
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if (regs->cp0_status & ST0_IEO)
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printk("IEo ");
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if (regs->cp0_status & ST0_KUP)
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printk("KUp ");
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if (regs->cp0_status & ST0_IEP)
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printk("IEp ");
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if (regs->cp0_status & ST0_KUC)
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printk("KUc ");
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if (regs->cp0_status & ST0_IEC)
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printk("IEc ");
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} else {
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if (regs->cp0_status & ST0_KX)
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printk("KX ");
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if (regs->cp0_status & ST0_SX)
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printk("SX ");
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if (regs->cp0_status & ST0_UX)
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printk("UX ");
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switch (regs->cp0_status & ST0_KSU) {
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case KSU_USER:
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printk("USER ");
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break;
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case KSU_SUPERVISOR:
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printk("SUPERVISOR ");
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break;
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case KSU_KERNEL:
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printk("KERNEL ");
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break;
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default:
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printk("BAD_MODE ");
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break;
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}
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if (regs->cp0_status & ST0_ERL)
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printk("ERL ");
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if (regs->cp0_status & ST0_EXL)
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printk("EXL ");
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if (regs->cp0_status & ST0_IE)
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printk("IE ");
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}
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printk("\n");
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printk("Cause : %08x\n", cause);
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cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
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if (1 <= cause && cause <= 5)
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printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
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printk("PrId : %08x\n", read_c0_prid());
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}
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void show_registers(struct pt_regs *regs)
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{
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show_regs(regs);
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print_modules();
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printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
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current->comm, current->pid, current_thread_info(), current);
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show_stack(current, (long *) regs->regs[29]);
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show_trace(current, (long *) regs->regs[29]);
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show_code((unsigned int *) regs->cp0_epc);
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printk("\n");
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}
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static DEFINE_SPINLOCK(die_lock);
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NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
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{
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static int die_counter;
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console_verbose();
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spin_lock_irq(&die_lock);
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printk("%s[#%d]:\n", str, ++die_counter);
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show_registers(regs);
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spin_unlock_irq(&die_lock);
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do_exit(SIGSEGV);
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}
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extern const struct exception_table_entry __start___dbe_table[];
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extern const struct exception_table_entry __stop___dbe_table[];
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void __declare_dbe_table(void)
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{
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__asm__ __volatile__(
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".section\t__dbe_table,\"a\"\n\t"
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".previous"
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);
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}
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/* Given an address, look for it in the exception tables. */
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static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
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{
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const struct exception_table_entry *e;
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e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
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if (!e)
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e = search_module_dbetables(addr);
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return e;
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}
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asmlinkage void do_be(struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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const struct exception_table_entry *fixup = NULL;
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int data = regs->cp0_cause & 4;
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int action = MIPS_BE_FATAL;
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/* XXX For now. Fixme, this searches the wrong table ... */
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if (data && !user_mode(regs))
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fixup = search_dbe_tables(exception_epc(regs));
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if (fixup)
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action = MIPS_BE_FIXUP;
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if (board_be_handler)
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action = board_be_handler(regs, fixup != 0);
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switch (action) {
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case MIPS_BE_DISCARD:
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return;
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case MIPS_BE_FIXUP:
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if (fixup) {
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regs->cp0_epc = fixup->nextinsn;
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return;
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}
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break;
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default:
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break;
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}
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/*
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* Assume it would be too dangerous to continue ...
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*/
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printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
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data ? "Data" : "Instruction",
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field, regs->cp0_epc, field, regs->regs[31]);
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die_if_kernel("Oops", regs);
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force_sig(SIGBUS, current);
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}
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static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
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{
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unsigned int __user *epc;
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epc = (unsigned int __user *) regs->cp0_epc +
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((regs->cp0_cause & CAUSEF_BD) != 0);
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if (!get_user(*opcode, epc))
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return 0;
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force_sig(SIGSEGV, current);
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return 1;
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}
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/*
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* ll/sc emulation
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*/
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#define OPCODE 0xfc000000
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#define BASE 0x03e00000
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#define RT 0x001f0000
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#define OFFSET 0x0000ffff
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#define LL 0xc0000000
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#define SC 0xe0000000
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#define SPEC3 0x7c000000
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#define RD 0x0000f800
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#define FUNC 0x0000003f
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#define RDHWR 0x0000003b
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/*
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* The ll_bit is cleared by r*_switch.S
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*/
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unsigned long ll_bit;
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static struct task_struct *ll_task = NULL;
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static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
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{
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unsigned long value, __user *vaddr;
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long offset;
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int signal = 0;
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/*
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* analyse the ll instruction that just caused a ri exception
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* and put the referenced address to addr.
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*/
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/* sign extend offset */
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offset = opcode & OFFSET;
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offset <<= 16;
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offset >>= 16;
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vaddr = (unsigned long __user *)
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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if ((unsigned long)vaddr & 3) {
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signal = SIGBUS;
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goto sig;
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}
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if (get_user(value, vaddr)) {
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signal = SIGSEGV;
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goto sig;
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}
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preempt_disable();
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if (ll_task == NULL || ll_task == current) {
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ll_bit = 1;
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} else {
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ll_bit = 0;
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}
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ll_task = current;
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preempt_enable();
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compute_return_epc(regs);
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regs->regs[(opcode & RT) >> 16] = value;
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return;
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sig:
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force_sig(signal, current);
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}
|
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|
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static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
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{
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unsigned long __user *vaddr;
|
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unsigned long reg;
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long offset;
|
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int signal = 0;
|
|
|
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/*
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* analyse the sc instruction that just caused a ri exception
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|
* and put the referenced address to addr.
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*/
|
|
|
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/* sign extend offset */
|
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offset = opcode & OFFSET;
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offset <<= 16;
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offset >>= 16;
|
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|
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vaddr = (unsigned long __user *)
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((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
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reg = (opcode & RT) >> 16;
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if ((unsigned long)vaddr & 3) {
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signal = SIGBUS;
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goto sig;
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}
|
|
|
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preempt_disable();
|
|
|
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if (ll_bit == 0 || ll_task != current) {
|
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compute_return_epc(regs);
|
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regs->regs[reg] = 0;
|
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preempt_enable();
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return;
|
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}
|
|
|
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preempt_enable();
|
|
|
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if (put_user(regs->regs[reg], vaddr)) {
|
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signal = SIGSEGV;
|
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goto sig;
|
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}
|
|
|
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compute_return_epc(regs);
|
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regs->regs[reg] = 1;
|
|
|
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return;
|
|
|
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sig:
|
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force_sig(signal, current);
|
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}
|
|
|
|
/*
|
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* ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
|
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* opcodes are supposed to result in coprocessor unusable exceptions if
|
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* executed on ll/sc-less processors. That's the theory. In practice a
|
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* few processors such as NEC's VR4100 throw reserved instruction exceptions
|
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* instead, so we're doing the emulation thing in both exception handlers.
|
|
*/
|
|
static inline int simulate_llsc(struct pt_regs *regs)
|
|
{
|
|
unsigned int opcode;
|
|
|
|
if (unlikely(get_insn_opcode(regs, &opcode)))
|
|
return -EFAULT;
|
|
|
|
if ((opcode & OPCODE) == LL) {
|
|
simulate_ll(regs, opcode);
|
|
return 0;
|
|
}
|
|
if ((opcode & OPCODE) == SC) {
|
|
simulate_sc(regs, opcode);
|
|
return 0;
|
|
}
|
|
|
|
return -EFAULT; /* Strange things going on ... */
|
|
}
|
|
|
|
/*
|
|
* Simulate trapping 'rdhwr' instructions to provide user accessible
|
|
* registers not implemented in hardware. The only current use of this
|
|
* is the thread area pointer.
|
|
*/
|
|
static inline int simulate_rdhwr(struct pt_regs *regs)
|
|
{
|
|
struct thread_info *ti = task_thread_info(current);
|
|
unsigned int opcode;
|
|
|
|
if (unlikely(get_insn_opcode(regs, &opcode)))
|
|
return -EFAULT;
|
|
|
|
if (unlikely(compute_return_epc(regs)))
|
|
return -EFAULT;
|
|
|
|
if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
|
|
int rd = (opcode & RD) >> 11;
|
|
int rt = (opcode & RT) >> 16;
|
|
switch (rd) {
|
|
case 29:
|
|
regs->regs[rt] = ti->tp_value;
|
|
return 0;
|
|
default:
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
|
|
/* Not ours. */
|
|
return -EFAULT;
|
|
}
|
|
|
|
asmlinkage void do_ov(struct pt_regs *regs)
|
|
{
|
|
siginfo_t info;
|
|
|
|
die_if_kernel("Integer overflow", regs);
|
|
|
|
info.si_code = FPE_INTOVF;
|
|
info.si_signo = SIGFPE;
|
|
info.si_errno = 0;
|
|
info.si_addr = (void __user *) regs->cp0_epc;
|
|
force_sig_info(SIGFPE, &info, current);
|
|
}
|
|
|
|
/*
|
|
* XXX Delayed fp exceptions when doing a lazy ctx switch XXX
|
|
*/
|
|
asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
|
|
{
|
|
if (fcr31 & FPU_CSR_UNI_X) {
|
|
int sig;
|
|
|
|
preempt_disable();
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
if (!is_fpu_owner()) {
|
|
/* We might lose fpu before disabling preempt... */
|
|
own_fpu();
|
|
BUG_ON(!used_math());
|
|
restore_fp(current);
|
|
}
|
|
#endif
|
|
/*
|
|
* Unimplemented operation exception. If we've got the full
|
|
* software emulator on-board, let's use it...
|
|
*
|
|
* Force FPU to dump state into task/thread context. We're
|
|
* moving a lot of data here for what is probably a single
|
|
* instruction, but the alternative is to pre-decode the FP
|
|
* register operands before invoking the emulator, which seems
|
|
* a bit extreme for what should be an infrequent event.
|
|
*/
|
|
save_fp(current);
|
|
/* Ensure 'resume' not overwrite saved fp context again. */
|
|
lose_fpu();
|
|
|
|
preempt_enable();
|
|
|
|
/* Run the emulator */
|
|
sig = fpu_emulator_cop1Handler (regs,
|
|
¤t->thread.fpu.soft);
|
|
|
|
preempt_disable();
|
|
|
|
own_fpu(); /* Using the FPU again. */
|
|
/*
|
|
* We can't allow the emulated instruction to leave any of
|
|
* the cause bit set in $fcr31.
|
|
*/
|
|
current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
|
|
|
|
/* Restore the hardware register state */
|
|
restore_fp(current);
|
|
|
|
preempt_enable();
|
|
|
|
/* If something went wrong, signal */
|
|
if (sig)
|
|
force_sig(sig, current);
|
|
|
|
return;
|
|
}
|
|
|
|
force_sig(SIGFPE, current);
|
|
}
|
|
|
|
asmlinkage void do_bp(struct pt_regs *regs)
|
|
{
|
|
unsigned int opcode, bcode;
|
|
siginfo_t info;
|
|
|
|
die_if_kernel("Break instruction in kernel code", regs);
|
|
|
|
if (get_insn_opcode(regs, &opcode))
|
|
return;
|
|
|
|
/*
|
|
* There is the ancient bug in the MIPS assemblers that the break
|
|
* code starts left to bit 16 instead to bit 6 in the opcode.
|
|
* Gas is bug-compatible, but not always, grrr...
|
|
* We handle both cases with a simple heuristics. --macro
|
|
*/
|
|
bcode = ((opcode >> 6) & ((1 << 20) - 1));
|
|
if (bcode < (1 << 10))
|
|
bcode <<= 10;
|
|
|
|
/*
|
|
* (A short test says that IRIX 5.3 sends SIGTRAP for all break
|
|
* insns, even for break codes that indicate arithmetic failures.
|
|
* Weird ...)
|
|
* But should we continue the brokenness??? --macro
|
|
*/
|
|
switch (bcode) {
|
|
case BRK_OVERFLOW << 10:
|
|
case BRK_DIVZERO << 10:
|
|
if (bcode == (BRK_DIVZERO << 10))
|
|
info.si_code = FPE_INTDIV;
|
|
else
|
|
info.si_code = FPE_INTOVF;
|
|
info.si_signo = SIGFPE;
|
|
info.si_errno = 0;
|
|
info.si_addr = (void __user *) regs->cp0_epc;
|
|
force_sig_info(SIGFPE, &info, current);
|
|
break;
|
|
default:
|
|
force_sig(SIGTRAP, current);
|
|
}
|
|
}
|
|
|
|
asmlinkage void do_tr(struct pt_regs *regs)
|
|
{
|
|
unsigned int opcode, tcode = 0;
|
|
siginfo_t info;
|
|
|
|
die_if_kernel("Trap instruction in kernel code", regs);
|
|
|
|
if (get_insn_opcode(regs, &opcode))
|
|
return;
|
|
|
|
/* Immediate versions don't provide a code. */
|
|
if (!(opcode & OPCODE))
|
|
tcode = ((opcode >> 6) & ((1 << 10) - 1));
|
|
|
|
/*
|
|
* (A short test says that IRIX 5.3 sends SIGTRAP for all trap
|
|
* insns, even for trap codes that indicate arithmetic failures.
|
|
* Weird ...)
|
|
* But should we continue the brokenness??? --macro
|
|
*/
|
|
switch (tcode) {
|
|
case BRK_OVERFLOW:
|
|
case BRK_DIVZERO:
|
|
if (tcode == BRK_DIVZERO)
|
|
info.si_code = FPE_INTDIV;
|
|
else
|
|
info.si_code = FPE_INTOVF;
|
|
info.si_signo = SIGFPE;
|
|
info.si_errno = 0;
|
|
info.si_addr = (void __user *) regs->cp0_epc;
|
|
force_sig_info(SIGFPE, &info, current);
|
|
break;
|
|
default:
|
|
force_sig(SIGTRAP, current);
|
|
}
|
|
}
|
|
|
|
asmlinkage void do_ri(struct pt_regs *regs)
|
|
{
|
|
die_if_kernel("Reserved instruction in kernel code", regs);
|
|
|
|
if (!cpu_has_llsc)
|
|
if (!simulate_llsc(regs))
|
|
return;
|
|
|
|
if (!simulate_rdhwr(regs))
|
|
return;
|
|
|
|
force_sig(SIGILL, current);
|
|
}
|
|
|
|
asmlinkage void do_cpu(struct pt_regs *regs)
|
|
{
|
|
unsigned int cpid;
|
|
|
|
die_if_kernel("do_cpu invoked from kernel context!", regs);
|
|
|
|
cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
|
|
|
|
switch (cpid) {
|
|
case 0:
|
|
if (!cpu_has_llsc)
|
|
if (!simulate_llsc(regs))
|
|
return;
|
|
|
|
if (!simulate_rdhwr(regs))
|
|
return;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
preempt_disable();
|
|
|
|
own_fpu();
|
|
if (used_math()) { /* Using the FPU again. */
|
|
restore_fp(current);
|
|
} else { /* First time FPU user. */
|
|
init_fpu();
|
|
set_used_math();
|
|
}
|
|
|
|
preempt_enable();
|
|
|
|
if (!cpu_has_fpu) {
|
|
int sig = fpu_emulator_cop1Handler(regs,
|
|
¤t->thread.fpu.soft);
|
|
if (sig)
|
|
force_sig(sig, current);
|
|
}
|
|
|
|
return;
|
|
|
|
case 2:
|
|
case 3:
|
|
break;
|
|
}
|
|
|
|
force_sig(SIGILL, current);
|
|
}
|
|
|
|
asmlinkage void do_mdmx(struct pt_regs *regs)
|
|
{
|
|
force_sig(SIGILL, current);
|
|
}
|
|
|
|
asmlinkage void do_watch(struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* We use the watch exception where available to detect stack
|
|
* overflows.
|
|
*/
|
|
dump_tlb_all();
|
|
show_regs(regs);
|
|
panic("Caught WATCH exception - probably caused by stack overflow.");
|
|
}
|
|
|
|
asmlinkage void do_mcheck(struct pt_regs *regs)
|
|
{
|
|
show_regs(regs);
|
|
dump_tlb_all();
|
|
/*
|
|
* Some chips may have other causes of machine check (e.g. SB1
|
|
* graduation timer)
|
|
*/
|
|
panic("Caught Machine Check exception - %scaused by multiple "
|
|
"matching entries in the TLB.",
|
|
(regs->cp0_status & ST0_TS) ? "" : "not ");
|
|
}
|
|
|
|
asmlinkage void do_mt(struct pt_regs *regs)
|
|
{
|
|
die_if_kernel("MIPS MT Thread exception in kernel", regs);
|
|
|
|
force_sig(SIGILL, current);
|
|
}
|
|
|
|
|
|
asmlinkage void do_dsp(struct pt_regs *regs)
|
|
{
|
|
if (cpu_has_dsp)
|
|
panic("Unexpected DSP exception\n");
|
|
|
|
force_sig(SIGILL, current);
|
|
}
|
|
|
|
asmlinkage void do_reserved(struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* Game over - no way to handle this if it ever occurs. Most probably
|
|
* caused by a new unknown cpu type or after another deadly
|
|
* hard/software error.
|
|
*/
|
|
show_regs(regs);
|
|
panic("Caught reserved exception %ld - should not happen.",
|
|
(regs->cp0_cause & 0x7f) >> 2);
|
|
}
|
|
|
|
asmlinkage void do_default_vi(struct pt_regs *regs)
|
|
{
|
|
show_regs(regs);
|
|
panic("Caught unexpected vectored interrupt.");
|
|
}
|
|
|
|
/*
|
|
* Some MIPS CPUs can enable/disable for cache parity detection, but do
|
|
* it different ways.
|
|
*/
|
|
static inline void parity_protection_init(void)
|
|
{
|
|
switch (current_cpu_data.cputype) {
|
|
case CPU_24K:
|
|
case CPU_5KC:
|
|
write_c0_ecc(0x80000000);
|
|
back_to_back_c0_hazard();
|
|
/* Set the PE bit (bit 31) in the c0_errctl register. */
|
|
printk(KERN_INFO "Cache parity protection %sabled\n",
|
|
(read_c0_ecc() & 0x80000000) ? "en" : "dis");
|
|
break;
|
|
case CPU_20KC:
|
|
case CPU_25KF:
|
|
/* Clear the DE bit (bit 16) in the c0_status register. */
|
|
printk(KERN_INFO "Enable cache parity protection for "
|
|
"MIPS 20KC/25KF CPUs.\n");
|
|
clear_c0_status(ST0_DE);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
asmlinkage void cache_parity_error(void)
|
|
{
|
|
const int field = 2 * sizeof(unsigned long);
|
|
unsigned int reg_val;
|
|
|
|
/* For the moment, report the problem and hang. */
|
|
printk("Cache error exception:\n");
|
|
printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
|
|
reg_val = read_c0_cacheerr();
|
|
printk("c0_cacheerr == %08x\n", reg_val);
|
|
|
|
printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
|
|
reg_val & (1<<30) ? "secondary" : "primary",
|
|
reg_val & (1<<31) ? "data" : "insn");
|
|
printk("Error bits: %s%s%s%s%s%s%s\n",
|
|
reg_val & (1<<29) ? "ED " : "",
|
|
reg_val & (1<<28) ? "ET " : "",
|
|
reg_val & (1<<26) ? "EE " : "",
|
|
reg_val & (1<<25) ? "EB " : "",
|
|
reg_val & (1<<24) ? "EI " : "",
|
|
reg_val & (1<<23) ? "E1 " : "",
|
|
reg_val & (1<<22) ? "E0 " : "");
|
|
printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
|
|
|
|
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
|
|
if (reg_val & (1<<22))
|
|
printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
|
|
|
|
if (reg_val & (1<<23))
|
|
printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
|
|
#endif
|
|
|
|
panic("Can't handle the cache error!");
|
|
}
|
|
|
|
/*
|
|
* SDBBP EJTAG debug exception handler.
|
|
* We skip the instruction and return to the next instruction.
|
|
*/
|
|
void ejtag_exception_handler(struct pt_regs *regs)
|
|
{
|
|
const int field = 2 * sizeof(unsigned long);
|
|
unsigned long depc, old_epc;
|
|
unsigned int debug;
|
|
|
|
printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
|
|
depc = read_c0_depc();
|
|
debug = read_c0_debug();
|
|
printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
|
|
if (debug & 0x80000000) {
|
|
/*
|
|
* In branch delay slot.
|
|
* We cheat a little bit here and use EPC to calculate the
|
|
* debug return address (DEPC). EPC is restored after the
|
|
* calculation.
|
|
*/
|
|
old_epc = regs->cp0_epc;
|
|
regs->cp0_epc = depc;
|
|
__compute_return_epc(regs);
|
|
depc = regs->cp0_epc;
|
|
regs->cp0_epc = old_epc;
|
|
} else
|
|
depc += 4;
|
|
write_c0_depc(depc);
|
|
|
|
#if 0
|
|
printk("\n\n----- Enable EJTAG single stepping ----\n\n");
|
|
write_c0_debug(debug | 0x100);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* NMI exception handler.
|
|
*/
|
|
void nmi_exception_handler(struct pt_regs *regs)
|
|
{
|
|
printk("NMI taken!!!!\n");
|
|
die("NMI", regs);
|
|
while(1) ;
|
|
}
|
|
|
|
#define VECTORSPACING 0x100 /* for EI/VI mode */
|
|
|
|
unsigned long ebase;
|
|
unsigned long exception_handlers[32];
|
|
unsigned long vi_handlers[64];
|
|
|
|
/*
|
|
* As a side effect of the way this is implemented we're limited
|
|
* to interrupt handlers in the address range from
|
|
* KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
|
|
*/
|
|
void *set_except_vector(int n, void *addr)
|
|
{
|
|
unsigned long handler = (unsigned long) addr;
|
|
unsigned long old_handler = exception_handlers[n];
|
|
|
|
exception_handlers[n] = handler;
|
|
if (n == 0 && cpu_has_divec) {
|
|
*(volatile u32 *)(ebase + 0x200) = 0x08000000 |
|
|
(0x03ffffff & (handler >> 2));
|
|
flush_icache_range(ebase + 0x200, ebase + 0x204);
|
|
}
|
|
return (void *)old_handler;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_MIPSR2
|
|
/*
|
|
* Shadow register allocation
|
|
* FIXME: SMP...
|
|
*/
|
|
|
|
/* MIPSR2 shadow register sets */
|
|
struct shadow_registers {
|
|
spinlock_t sr_lock; /* */
|
|
int sr_supported; /* Number of shadow register sets supported */
|
|
int sr_allocated; /* Bitmap of allocated shadow registers */
|
|
} shadow_registers;
|
|
|
|
void mips_srs_init(void)
|
|
{
|
|
#ifdef CONFIG_CPU_MIPSR2_SRS
|
|
shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
|
|
printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported);
|
|
#else
|
|
shadow_registers.sr_supported = 1;
|
|
#endif
|
|
shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
|
|
spin_lock_init(&shadow_registers.sr_lock);
|
|
}
|
|
|
|
int mips_srs_max(void)
|
|
{
|
|
return shadow_registers.sr_supported;
|
|
}
|
|
|
|
int mips_srs_alloc (void)
|
|
{
|
|
struct shadow_registers *sr = &shadow_registers;
|
|
unsigned long flags;
|
|
int set;
|
|
|
|
spin_lock_irqsave(&sr->sr_lock, flags);
|
|
|
|
for (set = 0; set < sr->sr_supported; set++) {
|
|
if ((sr->sr_allocated & (1 << set)) == 0) {
|
|
sr->sr_allocated |= 1 << set;
|
|
spin_unlock_irqrestore(&sr->sr_lock, flags);
|
|
return set;
|
|
}
|
|
}
|
|
|
|
/* None available */
|
|
spin_unlock_irqrestore(&sr->sr_lock, flags);
|
|
return -1;
|
|
}
|
|
|
|
void mips_srs_free (int set)
|
|
{
|
|
struct shadow_registers *sr = &shadow_registers;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sr->sr_lock, flags);
|
|
sr->sr_allocated &= ~(1 << set);
|
|
spin_unlock_irqrestore(&sr->sr_lock, flags);
|
|
}
|
|
|
|
void *set_vi_srs_handler (int n, void *addr, int srs)
|
|
{
|
|
unsigned long handler;
|
|
unsigned long old_handler = vi_handlers[n];
|
|
u32 *w;
|
|
unsigned char *b;
|
|
|
|
if (!cpu_has_veic && !cpu_has_vint)
|
|
BUG();
|
|
|
|
if (addr == NULL) {
|
|
handler = (unsigned long) do_default_vi;
|
|
srs = 0;
|
|
}
|
|
else
|
|
handler = (unsigned long) addr;
|
|
vi_handlers[n] = (unsigned long) addr;
|
|
|
|
b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
|
|
|
|
if (srs >= mips_srs_max())
|
|
panic("Shadow register set %d not supported", srs);
|
|
|
|
if (cpu_has_veic) {
|
|
if (board_bind_eic_interrupt)
|
|
board_bind_eic_interrupt (n, srs);
|
|
}
|
|
else if (cpu_has_vint) {
|
|
/* SRSMap is only defined if shadow sets are implemented */
|
|
if (mips_srs_max() > 1)
|
|
change_c0_srsmap (0xf << n*4, srs << n*4);
|
|
}
|
|
|
|
if (srs == 0) {
|
|
/*
|
|
* If no shadow set is selected then use the default handler
|
|
* that does normal register saving and a standard interrupt exit
|
|
*/
|
|
|
|
extern char except_vec_vi, except_vec_vi_lui;
|
|
extern char except_vec_vi_ori, except_vec_vi_end;
|
|
const int handler_len = &except_vec_vi_end - &except_vec_vi;
|
|
const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
|
|
const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
|
|
|
|
if (handler_len > VECTORSPACING) {
|
|
/*
|
|
* Sigh... panicing won't help as the console
|
|
* is probably not configured :(
|
|
*/
|
|
panic ("VECTORSPACING too small");
|
|
}
|
|
|
|
memcpy (b, &except_vec_vi, handler_len);
|
|
w = (u32 *)(b + lui_offset);
|
|
*w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
|
|
w = (u32 *)(b + ori_offset);
|
|
*w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
|
|
flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
|
|
}
|
|
else {
|
|
/*
|
|
* In other cases jump directly to the interrupt handler
|
|
*
|
|
* It is the handlers responsibility to save registers if required
|
|
* (eg hi/lo) and return from the exception using "eret"
|
|
*/
|
|
w = (u32 *)b;
|
|
*w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
|
|
*w = 0;
|
|
flush_icache_range((unsigned long)b, (unsigned long)(b+8));
|
|
}
|
|
|
|
return (void *)old_handler;
|
|
}
|
|
|
|
void *set_vi_handler (int n, void *addr)
|
|
{
|
|
return set_vi_srs_handler (n, addr, 0);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* This is used by native signal handling
|
|
*/
|
|
asmlinkage int (*save_fp_context)(struct sigcontext *sc);
|
|
asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
|
|
|
|
extern asmlinkage int _save_fp_context(struct sigcontext *sc);
|
|
extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
|
|
|
|
extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
|
|
extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
|
|
|
|
static inline void signal_init(void)
|
|
{
|
|
if (cpu_has_fpu) {
|
|
save_fp_context = _save_fp_context;
|
|
restore_fp_context = _restore_fp_context;
|
|
} else {
|
|
save_fp_context = fpu_emulator_save_context;
|
|
restore_fp_context = fpu_emulator_restore_context;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_MIPS32_COMPAT
|
|
|
|
/*
|
|
* This is used by 32-bit signal stuff on the 64-bit kernel
|
|
*/
|
|
asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
|
|
asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
|
|
|
|
extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
|
|
extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
|
|
|
|
extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
|
|
extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
|
|
|
|
static inline void signal32_init(void)
|
|
{
|
|
if (cpu_has_fpu) {
|
|
save_fp_context32 = _save_fp_context32;
|
|
restore_fp_context32 = _restore_fp_context32;
|
|
} else {
|
|
save_fp_context32 = fpu_emulator_save_context32;
|
|
restore_fp_context32 = fpu_emulator_restore_context32;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
extern void cpu_cache_init(void);
|
|
extern void tlb_init(void);
|
|
extern void flush_tlb_handlers(void);
|
|
|
|
void __init per_cpu_trap_init(void)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
unsigned int status_set = ST0_CU0;
|
|
|
|
/*
|
|
* Disable coprocessors and select 32-bit or 64-bit addressing
|
|
* and the 16/32 or 32/32 FPR register model. Reset the BEV
|
|
* flag that some firmware may have left set and the TS bit (for
|
|
* IP27). Set XX for ISA IV code to work.
|
|
*/
|
|
#ifdef CONFIG_64BIT
|
|
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
|
|
#endif
|
|
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
|
|
status_set |= ST0_XX;
|
|
change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
|
|
status_set);
|
|
|
|
if (cpu_has_dsp)
|
|
set_c0_status(ST0_MX);
|
|
|
|
#ifdef CONFIG_CPU_MIPSR2
|
|
write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
|
|
#endif
|
|
|
|
/*
|
|
* Interrupt handling.
|
|
*/
|
|
if (cpu_has_veic || cpu_has_vint) {
|
|
write_c0_ebase (ebase);
|
|
/* Setting vector spacing enables EI/VI mode */
|
|
change_c0_intctl (0x3e0, VECTORSPACING);
|
|
}
|
|
if (cpu_has_divec) {
|
|
if (cpu_has_mipsmt) {
|
|
unsigned int vpflags = dvpe();
|
|
set_c0_cause(CAUSEF_IV);
|
|
evpe(vpflags);
|
|
} else
|
|
set_c0_cause(CAUSEF_IV);
|
|
}
|
|
|
|
cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
|
|
TLBMISS_HANDLER_SETUP();
|
|
|
|
atomic_inc(&init_mm.mm_count);
|
|
current->active_mm = &init_mm;
|
|
BUG_ON(current->mm);
|
|
enter_lazy_tlb(&init_mm, current);
|
|
|
|
cpu_cache_init();
|
|
tlb_init();
|
|
}
|
|
|
|
/* Install CPU exception handler */
|
|
void __init set_handler (unsigned long offset, void *addr, unsigned long size)
|
|
{
|
|
memcpy((void *)(ebase + offset), addr, size);
|
|
flush_icache_range(ebase + offset, ebase + offset + size);
|
|
}
|
|
|
|
/* Install uncached CPU exception handler */
|
|
void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
|
|
{
|
|
#ifdef CONFIG_32BIT
|
|
unsigned long uncached_ebase = KSEG1ADDR(ebase);
|
|
#endif
|
|
#ifdef CONFIG_64BIT
|
|
unsigned long uncached_ebase = TO_UNCAC(ebase);
|
|
#endif
|
|
|
|
memcpy((void *)(uncached_ebase + offset), addr, size);
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
extern char except_vec3_generic, except_vec3_r4000;
|
|
extern char except_vec4;
|
|
unsigned long i;
|
|
|
|
if (cpu_has_veic || cpu_has_vint)
|
|
ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
|
|
else
|
|
ebase = CAC_BASE;
|
|
|
|
#ifdef CONFIG_CPU_MIPSR2
|
|
mips_srs_init();
|
|
#endif
|
|
|
|
per_cpu_trap_init();
|
|
|
|
/*
|
|
* Copy the generic exception handlers to their final destination.
|
|
* This will be overriden later as suitable for a particular
|
|
* configuration.
|
|
*/
|
|
set_handler(0x180, &except_vec3_generic, 0x80);
|
|
|
|
/*
|
|
* Setup default vectors
|
|
*/
|
|
for (i = 0; i <= 31; i++)
|
|
set_except_vector(i, handle_reserved);
|
|
|
|
/*
|
|
* Copy the EJTAG debug exception vector handler code to it's final
|
|
* destination.
|
|
*/
|
|
if (cpu_has_ejtag && board_ejtag_handler_setup)
|
|
board_ejtag_handler_setup ();
|
|
|
|
/*
|
|
* Only some CPUs have the watch exceptions.
|
|
*/
|
|
if (cpu_has_watch)
|
|
set_except_vector(23, handle_watch);
|
|
|
|
/*
|
|
* Initialise interrupt handlers
|
|
*/
|
|
if (cpu_has_veic || cpu_has_vint) {
|
|
int nvec = cpu_has_veic ? 64 : 8;
|
|
for (i = 0; i < nvec; i++)
|
|
set_vi_handler (i, NULL);
|
|
}
|
|
else if (cpu_has_divec)
|
|
set_handler(0x200, &except_vec4, 0x8);
|
|
|
|
/*
|
|
* Some CPUs can enable/disable for cache parity detection, but does
|
|
* it different ways.
|
|
*/
|
|
parity_protection_init();
|
|
|
|
/*
|
|
* The Data Bus Errors / Instruction Bus Errors are signaled
|
|
* by external hardware. Therefore these two exceptions
|
|
* may have board specific handlers.
|
|
*/
|
|
if (board_be_init)
|
|
board_be_init();
|
|
|
|
set_except_vector(1, handle_tlbm);
|
|
set_except_vector(2, handle_tlbl);
|
|
set_except_vector(3, handle_tlbs);
|
|
|
|
set_except_vector(4, handle_adel);
|
|
set_except_vector(5, handle_ades);
|
|
|
|
set_except_vector(6, handle_ibe);
|
|
set_except_vector(7, handle_dbe);
|
|
|
|
set_except_vector(8, handle_sys);
|
|
set_except_vector(9, handle_bp);
|
|
set_except_vector(10, handle_ri);
|
|
set_except_vector(11, handle_cpu);
|
|
set_except_vector(12, handle_ov);
|
|
set_except_vector(13, handle_tr);
|
|
|
|
if (current_cpu_data.cputype == CPU_R6000 ||
|
|
current_cpu_data.cputype == CPU_R6000A) {
|
|
/*
|
|
* The R6000 is the only R-series CPU that features a machine
|
|
* check exception (similar to the R4000 cache error) and
|
|
* unaligned ldc1/sdc1 exception. The handlers have not been
|
|
* written yet. Well, anyway there is no R6000 machine on the
|
|
* current list of targets for Linux/MIPS.
|
|
* (Duh, crap, there is someone with a triple R6k machine)
|
|
*/
|
|
//set_except_vector(14, handle_mc);
|
|
//set_except_vector(15, handle_ndc);
|
|
}
|
|
|
|
|
|
if (board_nmi_handler_setup)
|
|
board_nmi_handler_setup();
|
|
|
|
if (cpu_has_fpu && !cpu_has_nofpuex)
|
|
set_except_vector(15, handle_fpe);
|
|
|
|
set_except_vector(22, handle_mdmx);
|
|
|
|
if (cpu_has_mcheck)
|
|
set_except_vector(24, handle_mcheck);
|
|
|
|
if (cpu_has_mipsmt)
|
|
set_except_vector(25, handle_mt);
|
|
|
|
if (cpu_has_dsp)
|
|
set_except_vector(26, handle_dsp);
|
|
|
|
if (cpu_has_vce)
|
|
/* Special exception: R4[04]00 uses also the divec space. */
|
|
memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
|
|
else if (cpu_has_4kex)
|
|
memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
|
|
else
|
|
memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
|
|
|
|
signal_init();
|
|
#ifdef CONFIG_MIPS32_COMPAT
|
|
signal32_init();
|
|
#endif
|
|
|
|
flush_icache_range(ebase, ebase + 0x400);
|
|
flush_tlb_handlers();
|
|
}
|