forked from luck/tmp_suning_uos_patched
c658eac628
The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
166 lines
4.5 KiB
C
166 lines
4.5 KiB
C
/*
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* include/asm-xtensa/thread_info.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_THREAD_INFO_H
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#define _XTENSA_THREAD_INFO_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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# include <asm/processor.h>
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#endif
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/*
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* low level task data that entry.S needs immediate access to
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* - this struct should fit entirely inside of one cache line
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* - this struct shares the supervisor stack pages
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* - if the contents of this structure are changed, the assembly constants
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* must also be changed
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*/
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#ifndef __ASSEMBLY__
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#if XTENSA_HAVE_COPROCESSORS
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typedef struct xtregs_coprocessor {
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xtregs_cp0_t cp0;
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xtregs_cp1_t cp1;
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xtregs_cp2_t cp2;
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xtregs_cp3_t cp3;
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xtregs_cp4_t cp4;
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xtregs_cp5_t cp5;
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xtregs_cp6_t cp6;
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xtregs_cp7_t cp7;
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} xtregs_coprocessor_t;
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#endif
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struct thread_info {
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struct task_struct *task; /* main task structure */
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struct exec_domain *exec_domain; /* execution domain */
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unsigned long flags; /* low level flags */
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unsigned long status; /* thread-synchronous flags */
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__u32 cpu; /* current CPU */
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__s32 preempt_count; /* 0 => preemptable,< 0 => BUG*/
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mm_segment_t addr_limit; /* thread address space */
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struct restart_block restart_block;
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unsigned long cpenable;
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/* Allocate storage for extra user states and coprocessor states. */
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#if XTENSA_HAVE_COPROCESSORS
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xtregs_coprocessor_t xtregs_cp;
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#endif
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xtregs_user_t xtregs_user;
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};
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#else /* !__ASSEMBLY__ */
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/* offsets into the thread_info struct for assembly code access */
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#define TI_TASK 0x00000000
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#define TI_EXEC_DOMAIN 0x00000004
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#define TI_FLAGS 0x00000008
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#define TI_STATUS 0x0000000C
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#define TI_CPU 0x00000010
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#define TI_PRE_COUNT 0x00000014
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#define TI_ADDR_LIMIT 0x00000018
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#define TI_RESTART_BLOCK 0x000001C
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#endif
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#define PREEMPT_ACTIVE 0x10000000
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/*
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* macros/functions for gaining access to the thread information structure
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*
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* preempt_count needs to be 1 initially, until the scheduler is functional.
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*/
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#ifndef __ASSEMBLY__
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.exec_domain = &default_exec_domain, \
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.flags = 0, \
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.cpu = 0, \
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.preempt_count = 1, \
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.addr_limit = KERNEL_DS, \
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.restart_block = { \
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.fn = do_no_restart_syscall, \
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}, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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#define init_stack (init_thread_union.stack)
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/* how to get the thread information struct from C */
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static inline struct thread_info *current_thread_info(void)
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{
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struct thread_info *ti;
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__asm__("extui %0,a1,0,13\n\t"
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"xor %0, a1, %0" : "=&r" (ti) : );
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return ti;
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}
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/* thread information allocation */
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#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
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#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
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#else /* !__ASSEMBLY__ */
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/* how to get the thread information struct from ASM */
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#define GET_THREAD_INFO(reg,sp) \
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extui reg, sp, 0, 13; \
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xor reg, sp, reg
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#endif
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/*
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* thread information flags
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* - these are process state flags that various assembly files may need to access
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* - pending work-to-be-done flags are in LSW
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* - other flags in MSW
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*/
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#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
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#define TIF_SIGPENDING 1 /* signal pending */
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#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
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#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */
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#define TIF_IRET 4 /* return with iret */
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#define TIF_MEMDIE 5
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#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
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#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
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#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
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#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
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#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
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#define _TIF_IRET (1<<TIF_IRET)
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#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
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#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
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#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
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#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
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/*
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* Thread-synchronous status.
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*
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* This is different from the flags in that nobody else
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* ever touches our thread-synchronous status, so we don't
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* have to worry about atomic accesses.
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*/
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#define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */
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#define THREAD_SIZE 8192 //(2*PAGE_SIZE)
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_THREAD_INFO */
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