forked from luck/tmp_suning_uos_patched
cc9ca02a40
The power domains on the GX SoCs are very similar to G12A. The only known differences so far are: - The GX SoCs do not have the HHI_VPU_MEM_PD_REG2 register (for the VPU power-domain) - The GX SoCs have an additional reset line called "dvin" Add a new compatible string and adjust the reset line expectations for these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200515204709.1505498-3-martin.blumenstingl@googlemail.com
14 lines
298 B
C
14 lines
298 B
C
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H
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#define _DT_BINDINGS_MESON_GXBB_POWER_H
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#define PWRC_GXBB_VPU_ID 0
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#define PWRC_GXBB_ETHERNET_MEM_ID 1
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#endif
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