forked from luck/tmp_suning_uos_patched
f1b1eabff0
Right now, satellite frontend drivers specify frequencies in kHz, while terrestrial/cable ones specify in Hz. That's confusing for developers. However, the main problem is that universal frontends capable of handling both satellite and non-satelite delivery systems are appearing. We end by needing to hack the drivers in order to support such hybrid frontends. So, convert everything to specify frontend frequencies in Hz. Tested-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
607 lines
14 KiB
C
607 lines
14 KiB
C
/*
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* Driver for Zarlink DVB-T MT352 demodulator
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*
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* Written by Holger Waechtler <holger@qanu.de>
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* and Daniel Mack <daniel@qanu.de>
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*
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* AVerMedia AVerTV DVB-T 771 support by
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* Wolfram Joost <dbox2@frokaschwei.de>
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*
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* Support for Samsung TDTC9251DH01C(M) tuner
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* Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
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* Amauri Celani <acelani@essegi.net>
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*
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* DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
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* Christopher Pascoe <c.pascoe@itee.uq.edu.au>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <media/dvb_frontend.h>
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#include "mt352_priv.h"
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#include "mt352.h"
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struct mt352_state {
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struct i2c_adapter* i2c;
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struct dvb_frontend frontend;
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/* configuration settings */
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struct mt352_config config;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) printk(KERN_DEBUG "mt352: " args); \
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} while (0)
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static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
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{
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struct mt352_state* state = fe->demodulator_priv;
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u8 buf[2] = { reg, val };
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struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
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.buf = buf, .len = 2 };
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int err = i2c_transfer(state->i2c, &msg, 1);
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if (err != 1) {
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printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
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return err;
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}
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return 0;
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}
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static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
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{
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int err,i;
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for (i=0; i < ilen-1; i++)
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if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
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return err;
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return 0;
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}
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static int mt352_read_register(struct mt352_state* state, u8 reg)
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{
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int ret;
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u8 b0 [] = { reg };
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u8 b1 [] = { 0 };
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struct i2c_msg msg [] = { { .addr = state->config.demod_address,
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.flags = 0,
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.buf = b0, .len = 1 },
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{ .addr = state->config.demod_address,
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.flags = I2C_M_RD,
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.buf = b1, .len = 1 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) {
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printk("%s: readreg error (reg=%d, ret==%i)\n",
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__func__, reg, ret);
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return ret;
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}
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return b1[0];
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}
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static int mt352_sleep(struct dvb_frontend* fe)
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{
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static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
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_mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
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return 0;
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}
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static void mt352_calc_nominal_rate(struct mt352_state* state,
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u32 bandwidth,
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unsigned char *buf)
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{
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u32 adc_clock = 20480; /* 20.340 MHz */
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u32 bw,value;
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switch (bandwidth) {
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case 6000000:
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bw = 6;
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break;
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case 7000000:
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bw = 7;
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break;
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case 8000000:
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default:
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bw = 8;
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break;
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}
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if (state->config.adc_clock)
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adc_clock = state->config.adc_clock;
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value = 64 * bw * (1<<16) / (7 * 8);
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value = value * 1000 / adc_clock;
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dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
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__func__, bw, adc_clock, value);
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buf[0] = msb(value);
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buf[1] = lsb(value);
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}
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static void mt352_calc_input_freq(struct mt352_state* state,
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unsigned char *buf)
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{
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int adc_clock = 20480; /* 20.480000 MHz */
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int if2 = 36167; /* 36.166667 MHz */
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int ife,value;
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if (state->config.adc_clock)
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adc_clock = state->config.adc_clock;
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if (state->config.if2)
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if2 = state->config.if2;
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if (adc_clock >= if2 * 2)
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ife = if2;
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else {
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ife = adc_clock - (if2 % adc_clock);
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if (ife > adc_clock / 2)
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ife = adc_clock - ife;
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}
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value = -16374 * ife / adc_clock;
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dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
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__func__, if2, ife, adc_clock, value, value & 0x3fff);
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buf[0] = msb(value);
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buf[1] = lsb(value);
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}
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static int mt352_set_parameters(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *op = &fe->dtv_property_cache;
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struct mt352_state* state = fe->demodulator_priv;
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unsigned char buf[13];
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static unsigned char tuner_go[] = { 0x5d, 0x01 };
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static unsigned char fsm_go[] = { 0x5e, 0x01 };
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unsigned int tps = 0;
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switch (op->code_rate_HP) {
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case FEC_2_3:
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tps |= (1 << 7);
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break;
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case FEC_3_4:
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tps |= (2 << 7);
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break;
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case FEC_5_6:
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tps |= (3 << 7);
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break;
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case FEC_7_8:
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tps |= (4 << 7);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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default:
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return -EINVAL;
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}
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switch (op->code_rate_LP) {
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case FEC_2_3:
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tps |= (1 << 4);
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break;
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case FEC_3_4:
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tps |= (2 << 4);
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break;
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case FEC_5_6:
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tps |= (3 << 4);
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break;
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case FEC_7_8:
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tps |= (4 << 4);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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case FEC_NONE:
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if (op->hierarchy == HIERARCHY_AUTO ||
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op->hierarchy == HIERARCHY_NONE)
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break;
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/* fall through */
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default:
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return -EINVAL;
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}
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switch (op->modulation) {
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case QPSK:
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break;
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case QAM_AUTO:
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case QAM_16:
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tps |= (1 << 13);
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break;
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case QAM_64:
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tps |= (2 << 13);
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break;
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default:
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return -EINVAL;
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}
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switch (op->transmission_mode) {
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case TRANSMISSION_MODE_2K:
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case TRANSMISSION_MODE_AUTO:
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break;
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case TRANSMISSION_MODE_8K:
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tps |= (1 << 0);
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break;
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default:
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return -EINVAL;
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}
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switch (op->guard_interval) {
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case GUARD_INTERVAL_1_32:
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case GUARD_INTERVAL_AUTO:
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break;
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case GUARD_INTERVAL_1_16:
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tps |= (1 << 2);
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break;
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case GUARD_INTERVAL_1_8:
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tps |= (2 << 2);
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break;
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case GUARD_INTERVAL_1_4:
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tps |= (3 << 2);
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break;
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default:
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return -EINVAL;
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}
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switch (op->hierarchy) {
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case HIERARCHY_AUTO:
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case HIERARCHY_NONE:
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break;
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case HIERARCHY_1:
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tps |= (1 << 10);
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break;
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case HIERARCHY_2:
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tps |= (2 << 10);
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break;
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case HIERARCHY_4:
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tps |= (3 << 10);
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break;
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default:
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return -EINVAL;
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}
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buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
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buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
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buf[2] = lsb(tps);
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buf[3] = 0x50; // old
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// buf[3] = 0xf4; // pinnacle
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mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
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mt352_calc_input_freq(state, buf+6);
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if (state->config.no_tuner) {
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if (fe->ops.tuner_ops.set_params) {
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fe->ops.tuner_ops.set_params(fe);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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}
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_mt352_write(fe, buf, 8);
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_mt352_write(fe, fsm_go, 2);
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} else {
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if (fe->ops.tuner_ops.calc_regs) {
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fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
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buf[8] <<= 1;
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_mt352_write(fe, buf, sizeof(buf));
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_mt352_write(fe, tuner_go, 2);
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}
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}
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return 0;
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}
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static int mt352_get_parameters(struct dvb_frontend* fe,
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struct dtv_frontend_properties *op)
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{
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struct mt352_state* state = fe->demodulator_priv;
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u16 tps;
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u16 div;
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u8 trl;
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static const u8 tps_fec_to_api[8] =
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{
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FEC_1_2,
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FEC_2_3,
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FEC_3_4,
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FEC_5_6,
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FEC_7_8,
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FEC_AUTO,
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FEC_AUTO,
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FEC_AUTO
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};
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if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
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return -EINVAL;
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/* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
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* the mt352 sometimes works with the wrong parameters
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*/
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tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
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div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
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trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
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op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
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op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
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switch ( (tps >> 13) & 3)
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{
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case 0:
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op->modulation = QPSK;
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break;
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case 1:
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op->modulation = QAM_16;
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break;
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case 2:
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op->modulation = QAM_64;
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break;
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default:
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op->modulation = QAM_AUTO;
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break;
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}
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op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
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switch ( (tps >> 2) & 3)
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{
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case 0:
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op->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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op->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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op->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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op->guard_interval = GUARD_INTERVAL_1_4;
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break;
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default:
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op->guard_interval = GUARD_INTERVAL_AUTO;
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break;
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}
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switch ( (tps >> 10) & 7)
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{
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case 0:
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op->hierarchy = HIERARCHY_NONE;
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break;
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case 1:
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op->hierarchy = HIERARCHY_1;
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break;
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case 2:
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op->hierarchy = HIERARCHY_2;
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break;
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case 3:
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op->hierarchy = HIERARCHY_4;
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break;
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default:
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op->hierarchy = HIERARCHY_AUTO;
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break;
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}
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op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
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if (trl == 0x72)
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op->bandwidth_hz = 8000000;
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else if (trl == 0x64)
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op->bandwidth_hz = 7000000;
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else
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op->bandwidth_hz = 6000000;
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if (mt352_read_register(state, STATUS_2) & 0x02)
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op->inversion = INVERSION_OFF;
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else
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op->inversion = INVERSION_ON;
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return 0;
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}
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static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct mt352_state* state = fe->demodulator_priv;
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int s0, s1, s3;
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/* FIXME:
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*
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* The MT352 design manual from Zarlink states (page 46-47):
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*
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* Notes about the TUNER_GO register:
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*
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* If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
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* byte is copied from the tuner to the STATUS_3 register and
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* completion of the read operation is indicated by bit-5 of the
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* INTERRUPT_3 register.
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*/
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if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
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return -EREMOTEIO;
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if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
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return -EREMOTEIO;
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if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
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return -EREMOTEIO;
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*status = 0;
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if (s0 & (1 << 4))
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*status |= FE_HAS_CARRIER;
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if (s0 & (1 << 1))
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*status |= FE_HAS_VITERBI;
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if (s0 & (1 << 5))
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*status |= FE_HAS_LOCK;
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if (s1 & (1 << 1))
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*status |= FE_HAS_SYNC;
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if (s3 & (1 << 6))
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*status |= FE_HAS_SIGNAL;
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if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
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(FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
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*status &= ~FE_HAS_LOCK;
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return 0;
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}
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static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
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{
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struct mt352_state* state = fe->demodulator_priv;
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*ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
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(mt352_read_register (state, RS_ERR_CNT_1) << 8) |
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(mt352_read_register (state, RS_ERR_CNT_0));
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return 0;
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}
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static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
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{
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struct mt352_state* state = fe->demodulator_priv;
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/* align the 12 bit AGC gain with the most significant bits */
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u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
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(mt352_read_register(state, AGC_GAIN_0) << 4);
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/* inverse of gain is signal strength */
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*strength = ~signal;
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return 0;
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}
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static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
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{
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struct mt352_state* state = fe->demodulator_priv;
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u8 _snr = mt352_read_register (state, SNR);
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*snr = (_snr << 8) | _snr;
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return 0;
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}
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static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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{
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struct mt352_state* state = fe->demodulator_priv;
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*ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
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(mt352_read_register (state, RS_UBC_0));
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return 0;
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}
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static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
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{
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fe_tune_settings->min_delay_ms = 800;
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fe_tune_settings->step_size = 0;
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fe_tune_settings->max_drift = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt352_init(struct dvb_frontend* fe)
|
|
{
|
|
struct mt352_state* state = fe->demodulator_priv;
|
|
|
|
static u8 mt352_reset_attach [] = { RESET, 0xC0 };
|
|
|
|
dprintk("%s: hello\n",__func__);
|
|
|
|
if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
|
|
(mt352_read_register(state, CONFIG) & 0x20) == 0) {
|
|
|
|
/* Do a "hard" reset */
|
|
_mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
|
|
return state->config.demod_init(fe);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mt352_release(struct dvb_frontend* fe)
|
|
{
|
|
struct mt352_state* state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops mt352_ops;
|
|
|
|
struct dvb_frontend* mt352_attach(const struct mt352_config* config,
|
|
struct i2c_adapter* i2c)
|
|
{
|
|
struct mt352_state* state = NULL;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
|
|
if (state == NULL) goto error;
|
|
|
|
/* setup the state */
|
|
state->i2c = i2c;
|
|
memcpy(&state->config,config,sizeof(struct mt352_config));
|
|
|
|
/* check if the demod is there */
|
|
if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static const struct dvb_frontend_ops mt352_ops = {
|
|
.delsys = { SYS_DVBT },
|
|
.info = {
|
|
.name = "Zarlink MT352 DVB-T",
|
|
.frequency_min_hz = 174 * MHz,
|
|
.frequency_max_hz = 862 * MHz,
|
|
.frequency_stepsize_hz = 166667,
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
|
|
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
|
FE_CAN_FEC_AUTO |
|
|
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
|
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
|
|
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
|
|
FE_CAN_MUTE_TS
|
|
},
|
|
|
|
.release = mt352_release,
|
|
|
|
.init = mt352_init,
|
|
.sleep = mt352_sleep,
|
|
.write = _mt352_write,
|
|
|
|
.set_frontend = mt352_set_parameters,
|
|
.get_frontend = mt352_get_parameters,
|
|
.get_tune_settings = mt352_get_tune_settings,
|
|
|
|
.read_status = mt352_read_status,
|
|
.read_ber = mt352_read_ber,
|
|
.read_signal_strength = mt352_read_signal_strength,
|
|
.read_snr = mt352_read_snr,
|
|
.read_ucblocks = mt352_read_ucblocks,
|
|
};
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
|
|
|
MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
|
|
MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL(mt352_attach);
|