kernel_optimize_test/virt/kvm/arm
Christoffer Dall ae705930fc arm/arm64: KVM: Keep elrsr/aisr in sync with software model
There is an interesting bug in the vgic code, which manifests itself
when the KVM run loop has a signal pending or needs a vmid generation
rollover after having disabled interrupts but before actually switching
to the guest.

In this case, we flush the vgic as usual, but we sync back the vgic
state and exit to userspace before entering the guest.  The consequence
is that we will be syncing the list registers back to the software model
using the GICH_ELRSR and GICH_EISR from the last execution of the guest,
potentially overwriting a list register containing an interrupt.

This showed up during migration testing where we would capture a state
where the VM has masked the arch timer but there were no interrupts,
resulting in a hung test.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Reported-by: Alex Bennee <alex.bennee@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2015-03-14 13:42:07 +01:00
..
arch_timer.c timecounter: keep track of accumulated fractional nanoseconds 2014-12-30 18:29:27 -05:00
vgic-v2-emul.c arm/arm64: KVM: split GICv2 specific emulation code from vgic.c 2015-01-20 18:25:30 +01:00
vgic-v2.c arm/arm64: KVM: Keep elrsr/aisr in sync with software model 2015-03-14 13:42:07 +01:00
vgic-v3-emul.c arm/arm64: KVM: allow userland to request a virtual GICv3 2015-01-20 18:25:33 +01:00
vgic-v3.c arm/arm64: KVM: Keep elrsr/aisr in sync with software model 2015-03-14 13:42:07 +01:00
vgic.c arm/arm64: KVM: Keep elrsr/aisr in sync with software model 2015-03-14 13:42:07 +01:00
vgic.h arm/arm64: KVM: add virtual GICv3 distributor emulation 2015-01-20 18:25:31 +01:00