kernel_optimize_test/arch/xtensa/mm
Chris Zankel 0b2c3afdaa [XTENSA] Fix icache flush for cache aliasing
Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:08:18 -08:00
..
cache.c
fault.c
init.c
Makefile
misc.S
pgtable.c
tlb.c