forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* rtc and time ops for vr4181. Part of code is drived from
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* linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/param.h> /* for HZ */
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/vr4181/vr4181.h>
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#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
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/*
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* RTC ops
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*/
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DEFINE_SPINLOCK(rtc_lock);
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/* per VR41xx docs, bad data can be read if between 2 counts */
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static inline unsigned short
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read_time_reg(volatile unsigned short *reg)
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{
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unsigned short value;
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do {
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value = *reg;
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barrier();
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} while (value != *reg);
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return value;
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}
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static unsigned long
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vr4181_rtc_get_time(void)
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{
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unsigned short regh, regm, regl;
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// why this crazy order, you ask? to guarantee that neither m
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// nor l wrap before all 3 read
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do {
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regm = read_time_reg(VR4181_ETIMEMREG);
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barrier();
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regh = read_time_reg(VR4181_ETIMEHREG);
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barrier();
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regl = read_time_reg(VR4181_ETIMELREG);
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} while (regm != read_time_reg(VR4181_ETIMEMREG));
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return ((regh << 17) | (regm << 1) | (regl >> 15));
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}
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static int
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vr4181_rtc_set_time(unsigned long timeval)
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{
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unsigned short intreg;
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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intreg = *VR4181_RTCINTREG & 0x05;
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barrier();
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*VR4181_ETIMELREG = timeval << 15;
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*VR4181_ETIMEMREG = timeval >> 1;
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*VR4181_ETIMEHREG = timeval >> 17;
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barrier();
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// assume that any ints that just triggered are invalid, since the
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// time value is written non-atomically in 3 separate regs
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*VR4181_RTCINTREG = 0x05 ^ intreg;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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/*
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* timer interrupt routine (wrapper)
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*
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* we need our own interrupt routine because we need to clear
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* RTC1 interrupt.
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*/
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static void
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vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* Clear the interrupt. */
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*VR4181_RTCINTREG = 0x2;
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/* call the generic one */
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timer_interrupt(irq, dev_id, regs);
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}
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/*
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* vr4181_time_init:
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*
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* We pick the following choices:
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* . we use elapsed timer as the RTC. We set some reasonable init data since
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* it does not persist across reset
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* . we use RTC1 as the system timer interrupt source.
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* . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
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* frequency. In other words, we use calibrate_div64_gettimeoffset().
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* . we use our own timer interrupt routine which clears the interrupt
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* and then calls the generic high-level timer interrupt routine.
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*
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*/
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static void
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vr4181_timer_setup(struct irqaction *irq)
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{
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/* over-write the handler to be our own one */
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irq->handler = vr4181_timer_interrupt;
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/* sets up the frequency */
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*VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
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*VR4181_RTCL1HREG = 0;
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/* and ack any pending ints */
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*VR4181_RTCINTREG = 0x2;
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/* setup irqaction */
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setup_irq(VR4181_IRQ_INT1, irq);
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}
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void
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vr4181_init_time(void)
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{
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/* setup hookup functions */
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rtc_get_time = vr4181_rtc_get_time;
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rtc_set_time = vr4181_rtc_set_time;
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board_timer_setup = vr4181_timer_setup;
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}
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