forked from luck/tmp_suning_uos_patched
f18d533e3c
This implements initial support for the SMP INTC (particularly INTC2) controllers. These are largely implemented as conventional blocks, with register sets grouped together at fixed strides relative to the CPU id. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
#ifndef __ASM_SH_HW_IRQ_H
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#define __ASM_SH_HW_IRQ_H
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#include <linux/init.h>
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#include <asm/atomic.h>
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extern atomic_t irq_err_count;
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struct ipr_data {
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unsigned char irq;
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unsigned char ipr_idx; /* Index for the IPR registered */
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unsigned char shift; /* Number of bits to shift the data */
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unsigned char priority; /* The priority */
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};
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struct ipr_desc {
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unsigned long *ipr_offsets;
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unsigned int nr_offsets;
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struct ipr_data *ipr_data;
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unsigned int nr_irqs;
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struct irq_chip chip;
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};
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void register_ipr_controller(struct ipr_desc *);
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typedef unsigned char intc_enum;
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struct intc_vect {
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intc_enum enum_id;
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unsigned short vect;
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};
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
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struct intc_prio {
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intc_enum enum_id;
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unsigned char priority;
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};
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#define INTC_PRIO(enum_id, prio) { enum_id, prio }
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struct intc_group {
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intc_enum enum_id;
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intc_enum enum_ids[32];
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};
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#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width;
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intc_enum enum_ids[32];
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#ifdef CONFIG_SMP
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unsigned long smp;
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#endif
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};
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struct intc_prio_reg {
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unsigned long set_reg, clr_reg, reg_width, field_width;
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intc_enum enum_ids[16];
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#ifdef CONFIG_SMP
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unsigned long smp;
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#endif
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};
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struct intc_sense_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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#ifdef CONFIG_SMP
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#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
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#else
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#define INTC_SMP(stride, nr)
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#endif
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struct intc_desc {
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struct intc_vect *vectors;
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unsigned int nr_vectors;
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struct intc_group *groups;
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unsigned int nr_groups;
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struct intc_prio *priorities;
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unsigned int nr_priorities;
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struct intc_mask_reg *mask_regs;
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unsigned int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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unsigned int nr_prio_regs;
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struct intc_sense_reg *sense_regs;
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unsigned int nr_sense_regs;
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char *name;
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};
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#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
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#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
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priorities, mask_regs, prio_regs, sense_regs) \
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struct intc_desc symbol __initdata = { \
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_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
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_INTC_ARRAY(priorities), \
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_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
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_INTC_ARRAY(sense_regs), \
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chipname, \
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}
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void __init register_intc_controller(struct intc_desc *desc);
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int intc_set_priority(unsigned int irq, unsigned int prio);
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void __init plat_irq_setup(void);
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enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
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IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
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IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
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void __init plat_irq_setup_pins(int mode);
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#endif /* __ASM_SH_HW_IRQ_H */
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