forked from luck/tmp_suning_uos_patched
9287d95ea1
This patch is for supporting a new target platform, Renesas M32104UT evaluation board. The M32104UT is an eval board based on an uT-Engine specification. This board has an MMU-less M32R family processor, M32104. http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf This board is one of the most popular M32R platform, so we have ported Linux/M32R to it. Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
164 lines
5.6 KiB
C
164 lines
5.6 KiB
C
/*
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* include/asm/m32104ut/m32104ut_pld.h
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*
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* Definitions for Programable Logic Device(PLD) on M32104UT board.
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* Based on m32700ut_pld.h
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*
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* Copyright (c) 2002 Takeo Takahashi
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* Copyright (c) 2005 Naoto Sugai
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*/
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#ifndef _M32104UT_M32104UT_PLD_H
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#define _M32104UT_M32104UT_PLD_H
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#include <linux/config.h>
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#if defined(CONFIG_PLAT_M32104UT)
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#define PLD_PLAT_BASE 0x02c00000
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#else
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#error "no platform configuration"
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#endif
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#ifndef __ASSEMBLY__
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/*
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* C functions use non-cache address.
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*/
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#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
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#define __reg8 (volatile unsigned char *)
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#define __reg16 (volatile unsigned short *)
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#define __reg32 (volatile unsigned int *)
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#else
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#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
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#define __reg8
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#define __reg16
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#define __reg32
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#endif /* __ASSEMBLY__ */
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/* CFC */
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#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
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#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
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#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
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#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
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/* MMC */
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#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
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#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
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#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
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#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
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#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
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#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
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#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
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#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
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#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
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#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
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#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
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#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
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/* ICU
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* ICUISTS: status register
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* ICUIREQ0: request register
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* ICUIREQ1: request register
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* ICUCR3: control register for CFIREQ# interrupt
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* ICUCR4: control register for CFC Card insert interrupt
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* ICUCR5: control register for CFC Card eject interrupt
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* ICUCR6: control register for external interrupt
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* ICUCR11: control register for MMC Card insert/eject interrupt
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* ICUCR13: control register for SC error interrupt
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* ICUCR14: control register for SC receive interrupt
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* ICUCR15: control register for SC send interrupt
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*/
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#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */
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#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */
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#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */
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#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */
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#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */
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#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
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#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */
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#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */
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#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */
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#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
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#define PLD_ICUISTS_VECB_MASK (0xf000)
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#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
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#define PLD_ICUISTS_ISN_MASK (0x07c0)
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#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
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#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
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#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
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#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
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#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
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#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
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#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
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#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
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#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
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#define PLD_ICUCR_IEN (0x1000)
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#define PLD_ICUCR_IREQ (0x0100)
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#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
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#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
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#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
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#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
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#define PLD_ICUCR_ILEVEL0 (0x0000)
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#define PLD_ICUCR_ILEVEL1 (0x0001)
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#define PLD_ICUCR_ILEVEL2 (0x0002)
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#define PLD_ICUCR_ILEVEL3 (0x0003)
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#define PLD_ICUCR_ILEVEL4 (0x0004)
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#define PLD_ICUCR_ILEVEL5 (0x0005)
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#define PLD_ICUCR_ILEVEL6 (0x0006)
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#define PLD_ICUCR_ILEVEL7 (0x0007)
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/* Power Control of MMC and CF */
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#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
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#define PLD_CPCR_CDP 0x0001
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/* LED Control
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*
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* 1: DIP swich side
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* 2: Reset switch side
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*/
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#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
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#define PLD_IOLED_1_ON 0x001
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#define PLD_IOLED_1_OFF 0x000
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#define PLD_IOLED_2_ON 0x002
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#define PLD_IOLED_2_OFF 0x000
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/* DIP Switch
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* 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
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* 1: -
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* 2: -
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* 3: -
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*/
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#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
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#define PLD_IOSWSTS_IOSW2 0x0200
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#define PLD_IOSWSTS_IOSW1 0x0100
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#define PLD_IOSWSTS_IOWP0 0x0001
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/* CRC */
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#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
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#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
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#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
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#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
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#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
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#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
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/* RTC */
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#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
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#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
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#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
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#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
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#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
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/* SIM Card */
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#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
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#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
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#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
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#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
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#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
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#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
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#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
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#endif /* _M32104UT_M32104UT_PLD_H */
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