forked from luck/tmp_suning_uos_patched
ad09d58310
This patch is for supporting IDE interface for M3A-2170(Mappi-III) board. Signed-off-by: Mamoru Sakugawa <sakugawa@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
/*
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* include/asm/mappi3/mappi3_pld.h
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*
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* Definitions for Extended IO Logic on MAPPI3 board.
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* based on m32700ut_pld.h
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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*/
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#ifndef _MAPPI3_PLD_H
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#define _MAPPI3_PLD_H
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#ifndef __ASSEMBLY__
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/* FIXME:
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* Some C functions use non-cache address, so can't define non-cache address.
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*/
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#define PLD_BASE (0x1c000000 /* + NONCACHE_OFFSET */)
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#define __reg8 (volatile unsigned char *)
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#define __reg16 (volatile unsigned short *)
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#define __reg32 (volatile unsigned int *)
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#else
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#define PLD_BASE (0x1c000000 + NONCACHE_OFFSET)
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#define __reg8
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#define __reg16
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#define __reg32
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#endif /* __ASSEMBLY__ */
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/* CFC */
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#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
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#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
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#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
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#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
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#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
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#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
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/* MMC */
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#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
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#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
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#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
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#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
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#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
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#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
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#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
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#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
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#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
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#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
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#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
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#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
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/* Power Control of MMC and CF */
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#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
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/*==== ICU ====*/
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#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
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#define M32R_IRQ_I2C (28) /* I2C-BUS */
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#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
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#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */
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#define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */
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#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
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#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
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#if 0
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/* LED Control
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*
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* 1: DIP swich side
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* 2: Reset switch side
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*/
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#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
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#define PLD_IOLED_1_ON 0x001
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#define PLD_IOLED_1_OFF 0x000
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#define PLD_IOLED_2_ON 0x002
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#define PLD_IOLED_2_OFF 0x000
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/* DIP Switch
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* 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
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* 1: -
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* 2: -
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* 3: -
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*/
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#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
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#define PLD_IOSWSTS_IOSW2 0x0200
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#define PLD_IOSWSTS_IOSW1 0x0100
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#define PLD_IOSWSTS_IOWP0 0x0001
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#endif
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/* CRC */
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#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
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#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
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#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
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#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
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#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
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#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
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#if 0
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/* RTC */
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#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
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#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
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#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
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#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
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#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
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/* SIO0 */
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#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
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#define PLD_ESIO0CR_TXEN 0x0001
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#define PLD_ESIO0CR_RXEN 0x0002
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#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
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#define PLD_ESIO0MOD0_CTSS 0x0040
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#define PLD_ESIO0MOD0_RTSS 0x0080
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#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
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#define PLD_ESIO0MOD1_LMFS 0x0010
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#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
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#define PLD_ESIO0STS_TEMP 0x0001
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#define PLD_ESIO0STS_TXCP 0x0002
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#define PLD_ESIO0STS_RXCP 0x0004
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#define PLD_ESIO0STS_TXSC 0x0100
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#define PLD_ESIO0STS_RXSC 0x0200
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#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
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#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
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#define PLD_ESIO0INTCR_TXIEN 0x0002
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#define PLD_ESIO0INTCR_RXCEN 0x0004
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#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
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#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
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#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
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/* SIM Card */
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#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
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#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
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#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
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#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
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#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
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#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
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#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
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#endif
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#endif /* _MAPPI3_PLD.H */
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