forked from luck/tmp_suning_uos_patched
d5812a77e5
The handling of misaligned load/store multiple instructions did not check
to see if the address was ok to access before using __{get,put}_user().
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
411 lines
10 KiB
C
411 lines
10 KiB
C
/*
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* align.c - handle alignment exceptions for the Power PC.
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*
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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struct aligninfo {
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unsigned char len;
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unsigned char flags;
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};
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#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
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#define OPCD(inst) (((inst) & 0xFC000000) >> 26)
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#define RS(inst) (((inst) & 0x03E00000) >> 21)
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#define RA(inst) (((inst) & 0x001F0000) >> 16)
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#define IS_XFORM(code) ((code) == 31)
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#endif
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#define INVALID { 0, 0 }
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#define LD 1 /* load */
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#define ST 2 /* store */
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#define SE 4 /* sign-extend value */
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#define F 8 /* to/from fp regs */
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#define U 0x10 /* update index register */
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#define M 0x20 /* multiple load/store */
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#define S 0x40 /* single-precision fp, or byte-swap value */
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#define SX 0x40 /* byte count in XER */
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#define HARD 0x80 /* string, stwcx. */
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#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
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/*
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* The PowerPC stores certain bits of the instruction that caused the
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* alignment exception in the DSISR register. This array maps those
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* bits to information about the operand length and what the
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* instruction would do.
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*/
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static struct aligninfo aligninfo[128] = {
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{ 4, LD }, /* 00 0 0000: lwz / lwarx */
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INVALID, /* 00 0 0001 */
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{ 4, ST }, /* 00 0 0010: stw */
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INVALID, /* 00 0 0011 */
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{ 2, LD }, /* 00 0 0100: lhz */
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{ 2, LD+SE }, /* 00 0 0101: lha */
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{ 2, ST }, /* 00 0 0110: sth */
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{ 4, LD+M }, /* 00 0 0111: lmw */
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{ 4, LD+F+S }, /* 00 0 1000: lfs */
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{ 8, LD+F }, /* 00 0 1001: lfd */
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{ 4, ST+F+S }, /* 00 0 1010: stfs */
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{ 8, ST+F }, /* 00 0 1011: stfd */
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INVALID, /* 00 0 1100 */
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INVALID, /* 00 0 1101: ld/ldu/lwa */
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INVALID, /* 00 0 1110 */
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INVALID, /* 00 0 1111: std/stdu */
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{ 4, LD+U }, /* 00 1 0000: lwzu */
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INVALID, /* 00 1 0001 */
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{ 4, ST+U }, /* 00 1 0010: stwu */
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INVALID, /* 00 1 0011 */
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{ 2, LD+U }, /* 00 1 0100: lhzu */
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{ 2, LD+SE+U }, /* 00 1 0101: lhau */
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{ 2, ST+U }, /* 00 1 0110: sthu */
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{ 4, ST+M }, /* 00 1 0111: stmw */
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{ 4, LD+F+S+U }, /* 00 1 1000: lfsu */
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{ 8, LD+F+U }, /* 00 1 1001: lfdu */
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{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
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{ 8, ST+F+U }, /* 00 1 1011: stfdu */
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INVALID, /* 00 1 1100 */
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INVALID, /* 00 1 1101 */
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INVALID, /* 00 1 1110 */
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INVALID, /* 00 1 1111 */
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INVALID, /* 01 0 0000: ldx */
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INVALID, /* 01 0 0001 */
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INVALID, /* 01 0 0010: stdx */
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INVALID, /* 01 0 0011 */
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INVALID, /* 01 0 0100 */
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INVALID, /* 01 0 0101: lwax */
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INVALID, /* 01 0 0110 */
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INVALID, /* 01 0 0111 */
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{ 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
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{ 4, LD+M+HARD }, /* 01 0 1001: lswi */
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{ 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
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{ 4, ST+M+HARD }, /* 01 0 1011: stswi */
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INVALID, /* 01 0 1100 */
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INVALID, /* 01 0 1101 */
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INVALID, /* 01 0 1110 */
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INVALID, /* 01 0 1111 */
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INVALID, /* 01 1 0000: ldux */
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INVALID, /* 01 1 0001 */
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INVALID, /* 01 1 0010: stdux */
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INVALID, /* 01 1 0011 */
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INVALID, /* 01 1 0100 */
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INVALID, /* 01 1 0101: lwaux */
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INVALID, /* 01 1 0110 */
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INVALID, /* 01 1 0111 */
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INVALID, /* 01 1 1000 */
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INVALID, /* 01 1 1001 */
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INVALID, /* 01 1 1010 */
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INVALID, /* 01 1 1011 */
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INVALID, /* 01 1 1100 */
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INVALID, /* 01 1 1101 */
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INVALID, /* 01 1 1110 */
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INVALID, /* 01 1 1111 */
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INVALID, /* 10 0 0000 */
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INVALID, /* 10 0 0001 */
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{ 0, ST+HARD }, /* 10 0 0010: stwcx. */
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INVALID, /* 10 0 0011 */
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INVALID, /* 10 0 0100 */
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INVALID, /* 10 0 0101 */
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INVALID, /* 10 0 0110 */
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INVALID, /* 10 0 0111 */
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{ 4, LD+S }, /* 10 0 1000: lwbrx */
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INVALID, /* 10 0 1001 */
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{ 4, ST+S }, /* 10 0 1010: stwbrx */
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INVALID, /* 10 0 1011 */
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{ 2, LD+S }, /* 10 0 1100: lhbrx */
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INVALID, /* 10 0 1101 */
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{ 2, ST+S }, /* 10 0 1110: sthbrx */
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INVALID, /* 10 0 1111 */
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INVALID, /* 10 1 0000 */
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INVALID, /* 10 1 0001 */
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INVALID, /* 10 1 0010 */
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INVALID, /* 10 1 0011 */
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INVALID, /* 10 1 0100 */
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INVALID, /* 10 1 0101 */
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INVALID, /* 10 1 0110 */
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INVALID, /* 10 1 0111 */
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INVALID, /* 10 1 1000 */
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INVALID, /* 10 1 1001 */
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INVALID, /* 10 1 1010 */
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INVALID, /* 10 1 1011 */
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INVALID, /* 10 1 1100 */
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INVALID, /* 10 1 1101 */
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INVALID, /* 10 1 1110 */
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{ 0, ST+HARD }, /* 10 1 1111: dcbz */
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{ 4, LD }, /* 11 0 0000: lwzx */
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INVALID, /* 11 0 0001 */
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{ 4, ST }, /* 11 0 0010: stwx */
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INVALID, /* 11 0 0011 */
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{ 2, LD }, /* 11 0 0100: lhzx */
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{ 2, LD+SE }, /* 11 0 0101: lhax */
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{ 2, ST }, /* 11 0 0110: sthx */
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INVALID, /* 11 0 0111 */
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{ 4, LD+F+S }, /* 11 0 1000: lfsx */
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{ 8, LD+F }, /* 11 0 1001: lfdx */
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{ 4, ST+F+S }, /* 11 0 1010: stfsx */
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{ 8, ST+F }, /* 11 0 1011: stfdx */
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INVALID, /* 11 0 1100 */
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INVALID, /* 11 0 1101: lmd */
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INVALID, /* 11 0 1110 */
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INVALID, /* 11 0 1111: stmd */
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{ 4, LD+U }, /* 11 1 0000: lwzux */
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INVALID, /* 11 1 0001 */
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{ 4, ST+U }, /* 11 1 0010: stwux */
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INVALID, /* 11 1 0011 */
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{ 2, LD+U }, /* 11 1 0100: lhzux */
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{ 2, LD+SE+U }, /* 11 1 0101: lhaux */
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{ 2, ST+U }, /* 11 1 0110: sthux */
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INVALID, /* 11 1 0111 */
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{ 4, LD+F+S+U }, /* 11 1 1000: lfsux */
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{ 8, LD+F+U }, /* 11 1 1001: lfdux */
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{ 4, ST+F+S+U }, /* 11 1 1010: stfsux */
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{ 8, ST+F+U }, /* 11 1 1011: stfdux */
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INVALID, /* 11 1 1100 */
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INVALID, /* 11 1 1101 */
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INVALID, /* 11 1 1110 */
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INVALID, /* 11 1 1111 */
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};
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#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
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int
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fix_alignment(struct pt_regs *regs)
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{
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int instr, nb, flags;
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#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
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int opcode, f1, f2, f3;
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#endif
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int i, t;
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int reg, areg;
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int offset, nb0;
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unsigned char __user *addr;
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unsigned char *rptr;
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union {
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long l;
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float f;
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double d;
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unsigned char v[8];
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} data;
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CHECK_FULL_REGS(regs);
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#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
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/* The 4xx-family & Book-E processors have no DSISR register,
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* so we emulate it.
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* The POWER4 has a DSISR register but doesn't set it on
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* an alignment fault. -- paulus
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*/
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if (__get_user(instr, (unsigned int __user *) regs->nip))
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return 0;
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opcode = OPCD(instr);
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reg = RS(instr);
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areg = RA(instr);
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if (!IS_XFORM(opcode)) {
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f1 = 0;
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f2 = (instr & 0x04000000) >> 26;
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f3 = (instr & 0x78000000) >> 27;
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} else {
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f1 = (instr & 0x00000006) >> 1;
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f2 = (instr & 0x00000040) >> 6;
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f3 = (instr & 0x00000780) >> 7;
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}
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instr = ((f1 << 5) | (f2 << 4) | f3);
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#else
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reg = (regs->dsisr >> 5) & 0x1f; /* source/dest register */
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areg = regs->dsisr & 0x1f; /* register to update */
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instr = (regs->dsisr >> 10) & 0x7f;
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#endif
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nb = aligninfo[instr].len;
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if (nb == 0) {
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long __user *p;
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int i;
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if (instr != DCBZ)
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return 0; /* too hard or invalid instruction */
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/*
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* The dcbz (data cache block zero) instruction
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* gives an alignment fault if used on non-cacheable
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* memory. We handle the fault mainly for the
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* case when we are running with the cache disabled
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* for debugging.
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*/
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p = (long __user *) (regs->dar & -L1_CACHE_BYTES);
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if (user_mode(regs)
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&& !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))
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return -EFAULT;
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for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
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if (__put_user(0, p+i))
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return -EFAULT;
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return 1;
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}
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flags = aligninfo[instr].flags;
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if ((flags & (LD|ST)) == 0)
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return 0;
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/* For the 4xx-family & Book-E processors, the 'dar' field of the
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* pt_regs structure is overloaded and is really from the DEAR.
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*/
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addr = (unsigned char __user *)regs->dar;
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if (flags & M) {
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/* lmw, stmw, lswi/x, stswi/x */
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nb0 = 0;
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if (flags & HARD) {
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if (flags & SX) {
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nb = regs->xer & 127;
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if (nb == 0)
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return 1;
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} else {
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if (__get_user(instr,
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(unsigned int __user *)regs->nip))
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return 0;
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nb = (instr >> 11) & 0x1f;
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if (nb == 0)
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nb = 32;
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}
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if (nb + reg * 4 > 128) {
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nb0 = nb + reg * 4 - 128;
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nb = 128 - reg * 4;
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}
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} else {
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/* lwm, stmw */
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nb = (32 - reg) * 4;
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}
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if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
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return -EFAULT; /* bad address */
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rptr = (unsigned char *) ®s->gpr[reg];
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if (flags & LD) {
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for (i = 0; i < nb; ++i)
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if (__get_user(rptr[i], addr+i))
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return -EFAULT;
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if (nb0 > 0) {
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rptr = (unsigned char *) ®s->gpr[0];
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addr += nb;
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for (i = 0; i < nb0; ++i)
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if (__get_user(rptr[i], addr+i))
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return -EFAULT;
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}
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for (; (i & 3) != 0; ++i)
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rptr[i] = 0;
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} else {
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for (i = 0; i < nb; ++i)
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if (__put_user(rptr[i], addr+i))
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return -EFAULT;
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if (nb0 > 0) {
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rptr = (unsigned char *) ®s->gpr[0];
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addr += nb;
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for (i = 0; i < nb0; ++i)
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if (__put_user(rptr[i], addr+i))
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return -EFAULT;
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}
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}
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return 1;
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}
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offset = 0;
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if (nb < 4) {
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/* read/write the least significant bits */
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data.l = 0;
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offset = 4 - nb;
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}
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/* Verify the address of the operand */
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if (user_mode(regs)) {
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if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
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return -EFAULT; /* bad address */
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}
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if (flags & F) {
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preempt_disable();
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if (regs->msr & MSR_FP)
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giveup_fpu(current);
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preempt_enable();
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}
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/* If we read the operand, copy it in, else get register values */
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if (flags & LD) {
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for (i = 0; i < nb; ++i)
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if (__get_user(data.v[offset+i], addr+i))
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return -EFAULT;
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} else if (flags & F) {
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data.d = current->thread.fpr[reg];
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} else {
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data.l = regs->gpr[reg];
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}
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switch (flags & ~U) {
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case LD+SE: /* sign extend */
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if (data.v[2] >= 0x80)
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data.v[0] = data.v[1] = -1;
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break;
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case LD+S: /* byte-swap */
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case ST+S:
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if (nb == 2) {
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SWAP(data.v[2], data.v[3]);
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} else {
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SWAP(data.v[0], data.v[3]);
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SWAP(data.v[1], data.v[2]);
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}
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break;
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/* Single-precision FP load and store require conversions... */
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case LD+F+S:
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#ifdef CONFIG_PPC_FPU
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preempt_disable();
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enable_kernel_fp();
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cvt_fd(&data.f, &data.d, ¤t->thread.fpscr);
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preempt_enable();
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#else
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return 0;
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#endif
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break;
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case ST+F+S:
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#ifdef CONFIG_PPC_FPU
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preempt_disable();
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enable_kernel_fp();
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cvt_df(&data.d, &data.f, ¤t->thread.fpscr);
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preempt_enable();
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#else
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return 0;
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#endif
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break;
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}
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if (flags & ST) {
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for (i = 0; i < nb; ++i)
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if (__put_user(data.v[offset+i], addr+i))
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return -EFAULT;
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} else if (flags & F) {
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current->thread.fpr[reg] = data.d;
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} else {
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regs->gpr[reg] = data.l;
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}
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if (flags & U)
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regs->gpr[areg] = regs->dar;
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return 1;
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}
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