Dinh Nguyen 45be0cdb53 ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ... Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>		2015-06-10 15:35:35 -07:00
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core.h	ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10	2015-06-10 15:35:35 -07:00
headsmp.S	ARM: socfpga: enable big endian for secondary core(s)	2015-05-11 13:59:23 -05:00
Kconfig	ARM: socfpga: support big endian for socfpga	2015-05-11 13:59:23 -05:00
Makefile	ARM: socfpga: Enable SMP for socfpga	2012-10-26 14:59:39 +02:00
platsmp.c	ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10	2015-06-10 15:35:35 -07:00
socfpga.c	ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5	2015-06-10 15:35:34 -07:00