forked from luck/tmp_suning_uos_patched
52393ccc0a
set_wmb should not be used in the kernel because it just confuses the
code more and has no benefit. Since it is not currently used in the
kernel this patch removes it so that new code does not include it.
All archs define set_wmb(var, value) to do { var = value; wmb(); }
while(0) except ia64 and sparc which use a mb() instead. But this is
still moot since it is not used anyway.
Hasn't been tested on any archs but x86 and x86_64 (and only compiled
tested)
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
340 lines
8.8 KiB
C
340 lines
8.8 KiB
C
#ifndef _M68KNOMMU_SYSTEM_H
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#define _M68KNOMMU_SYSTEM_H
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/entry.h>
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/*
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* switch_to(n) should switch tasks to task ptr, first checking that
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* ptr isn't the current task, in which case it does nothing. This
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* also clears the TS-flag if the task we switched to has used the
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* math co-processor latest.
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*/
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/*
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* switch_to() saves the extra registers, that are not saved
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* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
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* a0-a1. Some of these are used by schedule() and its predecessors
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* and so we might get see unexpected behaviors when a task returns
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* with unexpected register values.
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*
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* syscall stores these registers itself and none of them are used
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* by syscall after the function in the syscall has been called.
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*
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* Beware that resume now expects *next to be in d1 and the offset of
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* tss to be in a1. This saves a few instructions as we no longer have
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* to push them onto the stack and read them back right after.
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*
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* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
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*
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* Changed 96/09/19 by Andreas Schwab
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* pass prev in a0, next in a1, offset of tss in d1, and whether
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* the mm structures are shared in d2 (to avoid atc flushing).
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*/
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asmlinkage void resume(void);
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#define switch_to(prev,next,last) \
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{ \
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void *_last; \
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__asm__ __volatile__( \
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"movel %1, %%a0\n\t" \
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"movel %2, %%a1\n\t" \
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"jbsr resume\n\t" \
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"movel %%d1, %0\n\t" \
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: "=d" (_last) \
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: "d" (prev), "d" (next) \
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: "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
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(last) = _last; \
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}
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#ifdef CONFIG_COLDFIRE
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#define local_irq_enable() __asm__ __volatile__ ( \
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"move %/sr,%%d0\n\t" \
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"andi.l #0xf8ff,%%d0\n\t" \
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"move %%d0,%/sr\n" \
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: /* no outputs */ \
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: \
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: "cc", "%d0", "memory")
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#define local_irq_disable() __asm__ __volatile__ ( \
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"move %/sr,%%d0\n\t" \
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"ori.l #0x0700,%%d0\n\t" \
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"move %%d0,%/sr\n" \
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: /* no outputs */ \
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: \
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: "cc", "%d0", "memory")
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/* For spinlocks etc */
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#define local_irq_save(x) __asm__ __volatile__ ( \
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"movew %%sr,%0\n\t" \
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"movew #0x0700,%%d0\n\t" \
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"or.l %0,%%d0\n\t" \
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"movew %%d0,%/sr" \
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: "=d" (x) \
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: \
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: "cc", "%d0", "memory")
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#else
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/* portable version */ /* FIXME - see entry.h*/
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#define ALLOWINT 0xf8ff
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#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
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#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
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#endif
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#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
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#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
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/* For spinlocks etc */
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#ifndef local_irq_save
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#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
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#endif
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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((flags & 0x0700) == 0x0700); \
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})
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#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
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/*
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* Force strict CPU ordering.
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* Not really required on m68k...
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*/
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#define nop() asm volatile ("nop"::)
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#define mb() asm volatile ("" : : :"memory")
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#define rmb() asm volatile ("" : : :"memory")
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#define wmb() asm volatile ("" : : :"memory")
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#define set_rmb(var, value) do { xchg(&var, value); } while (0)
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#define set_mb(var, value) set_rmb(var, value)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((volatile struct __xchg_dummy *)(x))
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#ifndef CONFIG_RMW_INSNS
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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unsigned long tmp, flags;
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local_irq_save(flags);
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"moveb %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"movew %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"movel %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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}
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local_irq_restore(flags);
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return tmp;
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}
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#else
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"1:\n\t"
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"casb %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"1:\n\t"
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"casw %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"1:\n\t"
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"casl %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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}
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return x;
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}
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#endif
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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cmpxchg(volatile int *p, int old, int new)
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{
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unsigned long flags;
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int prev;
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local_irq_save(flags);
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if ((prev = *p) == old)
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*p = new;
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local_irq_restore(flags);
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return(prev);
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}
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#ifdef CONFIG_M68332
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#define HARD_RESET_NOW() ({ \
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local_irq_disable(); \
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asm(" \
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movew #0x0000, 0xfffa6a; \
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reset; \
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/*movew #0x1557, 0xfffa44;*/ \
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/*movew #0x0155, 0xfffa46;*/ \
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moveal #0, %a0; \
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movec %a0, %vbr; \
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moveal 0, %sp; \
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moveal 4, %a0; \
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jmp (%a0); \
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"); \
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})
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#endif
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#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
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defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
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#define HARD_RESET_NOW() ({ \
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local_irq_disable(); \
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asm(" \
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moveal #0x10c00000, %a0; \
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moveb #0, 0xFFFFF300; \
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moveal 0(%a0), %sp; \
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moveal 4(%a0), %a0; \
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jmp (%a0); \
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"); \
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})
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#endif
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#ifdef CONFIG_COLDFIRE
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#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
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/*
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* Need to account for broken early mask of 5272 silicon. So don't
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* jump through the original start address. Jump strait into the
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* known start of the FLASH code.
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*/
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#define HARD_RESET_NOW() ({ \
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asm(" \
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movew #0x2700, %sr; \
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jmp 0xf0000400; \
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"); \
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})
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#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
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defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) || \
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defined(CONFIG_CLEOPATRA)
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#define HARD_RESET_NOW() ({ \
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asm(" \
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movew #0x2700, %sr; \
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moveal #0x10000044, %a0; \
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movel #0xffffffff, (%a0); \
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moveal #0x10000001, %a0; \
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moveb #0x00, (%a0); \
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moveal #0xf0000004, %a0; \
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moveal (%a0), %a0; \
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jmp (%a0); \
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"); \
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})
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#elif defined(CONFIG_M5272)
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/*
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* Retrieve the boot address in flash using CSBR0 and CSOR0
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* find the reset vector at flash_address + 4 (e.g. 0x400)
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* remap it in the flash's current location (e.g. 0xf0000400)
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* and jump there.
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*/
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#define HARD_RESET_NOW() ({ \
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asm(" \
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movew #0x2700, %%sr; \
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move.l %0+0x40,%%d0; \
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and.l %0+0x44,%%d0; \
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andi.l #0xfffff000,%%d0; \
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mov.l %%d0,%%a0; \
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or.l 4(%%a0),%%d0; \
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mov.l %%d0,%%a0; \
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jmp (%%a0);" \
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: /* No output */ \
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: "o" (*(char *)MCF_MBAR) ); \
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})
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#elif defined(CONFIG_M528x)
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/*
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* The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
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* that when set, resets the MCF528x.
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*/
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#define HARD_RESET_NOW() \
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({ \
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unsigned char volatile *reset; \
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asm("move.w #0x2700, %sr"); \
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reset = ((volatile unsigned short *)(MCF_IPSBAR + 0x110000)); \
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while(1) \
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*reset |= (0x01 << 7);\
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})
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#elif defined(CONFIG_M523x)
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#define HARD_RESET_NOW() ({ \
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asm(" \
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movew #0x2700, %sr; \
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movel #0x01000000, %sp; \
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moveal #0x40110000, %a0; \
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moveb #0x80, (%a0); \
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"); \
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})
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#elif defined(CONFIG_M520x)
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/*
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* The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
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* RCR), that when set, resets the MCF5208.
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*/
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#define HARD_RESET_NOW() \
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({ \
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unsigned char volatile *reset; \
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asm("move.w #0x2700, %sr"); \
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reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000)); \
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while(1) \
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*reset |= 0x80; \
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})
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#else
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#define HARD_RESET_NOW() ({ \
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asm(" \
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movew #0x2700, %sr; \
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moveal #0x4, %a0; \
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moveal (%a0), %a0; \
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jmp (%a0); \
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"); \
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})
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#endif
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#endif
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#define arch_align_stack(x) (x)
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#endif /* _M68KNOMMU_SYSTEM_H */
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