forked from luck/tmp_suning_uos_patched
1a4baafa7d
The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
228 lines
5.3 KiB
ArmAsm
228 lines
5.3 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-sa110.S
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*
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* Copyright (C) 1997-2002 Russell King
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for SA110
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the StrongARM-110.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <mach/hardware.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* the cache line size of the I and D cache
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*/
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#define DCACHELINESIZE 32
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.text
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/*
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* cpu_sa110_proc_init()
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*/
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ENTRY(cpu_sa110_proc_init)
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mov r0, #0
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mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
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mov pc, lr
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/*
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* cpu_sa110_proc_fin()
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*/
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ENTRY(cpu_sa110_proc_fin)
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mov r0, #0
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mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_sa110_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_sa110_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_sa110_reset)
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.popsection
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/*
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* cpu_sa110_do_idle(type)
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*
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* Cause the processor to idle
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*
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* type: call type:
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* 0 = slow idle
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* 1 = fast idle
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* 2 = switch to slow processor clock
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* 3 = switch to fast processor clock
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*/
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.align 5
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ENTRY(cpu_sa110_do_idle)
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mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
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ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
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ldr r1, [r1, #0] @ force switch to MCLK
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mov r0, r0 @ safety
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mov r0, r0 @ safety
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mov r0, r0 @ safety
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mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
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mov r0, r0 @ safety
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mov r0, r0 @ safety
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mov r0, r0 @ safety
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mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
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mov pc, lr
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/* ================================= CACHE ================================ */
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/*
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* cpu_sa110_dcache_clean_area(addr,sz)
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*
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* Clean the specified entry of any caches such that the MMU
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* translation fetches will obtain correct data.
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*
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* addr: cache-unaligned virtual address
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*/
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.align 5
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ENTRY(cpu_sa110_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #DCACHELINESIZE
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subs r1, r1, #DCACHELINESIZE
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bhi 1b
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_sa110_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_sa110_switch_mm)
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#ifdef CONFIG_MMU
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str lr, [sp, #-4]!
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bl v4wb_flush_kern_cache_all @ clears IP
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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ldr pc, [sp], #4
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#else
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mov pc, lr
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#endif
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/*
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* cpu_sa110_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_sa110_set_pte_ext)
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#ifdef CONFIG_MMU
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armv3_set_pte_ext wc_disable=0
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mov r0, r0
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mov pc, lr
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__CPUINIT
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.type __sa110_setup, #function
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__sa110_setup:
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mov r10, #0
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mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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adr r5, sa110_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0 @ get control register v4
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bic r0, r0, r5
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orr r0, r0, r6
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mov pc, lr
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.size __sa110_setup, . - __sa110_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* ..01 0001 ..11 1101
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*
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*/
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.type sa110_crval, #object
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sa110_crval:
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crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
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.section ".rodata"
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string cpu_arch_name, "armv4"
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string cpu_elf_name, "v4"
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string cpu_sa110_name, "StrongARM-110"
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __sa110_proc_info,#object
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__sa110_proc_info:
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.long 0x4401a100
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __sa110_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
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.long cpu_sa110_name
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.long sa110_processor_functions
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.long v4wb_tlb_fns
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.long v4wb_user_fns
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.long v4wb_cache_fns
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.size __sa110_proc_info, . - __sa110_proc_info
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